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-- Description : Testbench instantiates core, data memory, instruction memory
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-- Description : Testbench instantiates core, data memory, instruction memory
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-- and a character device.
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-- and a character device.
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--
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--
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.ALL;
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use ieee.std_logic_unsigned.all;
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LIBRARY mblite;
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library mblite;
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USE mblite.config_Pkg.ALL;
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use mblite.config_Pkg.all;
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USE mblite.core_Pkg.ALL;
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use mblite.core_Pkg.all;
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USE mblite.std_Pkg.ALL;
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use mblite.std_Pkg.all;
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use std.textio.all;
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use std.textio.all;
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ENTITY testbench IS
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entity testbench is
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END testbench;
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end testbench;
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ARCHITECTURE arch OF testbench IS
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architecture arch of testbench is
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SIGNAL imem_o : imem_out_type;
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signal imem_o : imem_out_type;
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SIGNAL imem_i : imem_in_type;
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signal imem_i : imem_in_type;
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SIGNAL wb_o : wb_mst_out_type;
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signal wb_o : wb_mst_out_type;
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SIGNAL wb_i : wb_mst_in_type;
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signal wb_i : wb_mst_in_type;
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SIGNAL sys_clk_i : std_logic := '0';
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signal sys_clk_i : std_logic := '0';
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SIGNAL sys_int_i : std_logic;
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signal sys_int_i : std_logic;
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SIGNAL sys_rst_i : std_logic;
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signal sys_rst_i : std_logic;
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CONSTANT std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
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constant std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0) := X"FFFFFFC0";
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SIGNAL std_out_ack : std_logic;
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signal std_out_ack : std_logic;
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SIGNAL stdo_ena : std_logic;
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signal stdo_ena : std_logic;
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SIGNAL dmem_ena : std_logic;
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signal dmem_ena : std_logic;
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SIGNAL dmem_dat : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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signal dmem_dat : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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SIGNAL dmem_sel : std_logic_vector(3 DOWNTO 0);
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signal dmem_sel : std_logic_vector(3 downto 0);
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CONSTANT rom_size : integer := 16;
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constant rom_size : integer := 16;
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CONSTANT ram_size : integer := 16;
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constant ram_size : integer := 16;
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BEGIN
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begin
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sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
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sys_clk_i <= not sys_clk_i after 10000 ps;
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sys_rst_i <= '1' AFTER 0 ps, '0' AFTER 150000 ps;
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sys_rst_i <= '1' after 0 ps, '0' after 150000 ps;
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sys_int_i <= '1' AFTER 500000000 ps, '0' after 500040000 ps;
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sys_int_i <= '1' after 500000000 ps, '0' after 500040000 ps;
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timeout: PROCESS(sys_clk_i)
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timeout: process(sys_clk_i)
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BEGIN
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begin
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IF NOW = 10 ms THEN
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if NOW = 10 ms then
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report "TIMEOUT" SEVERITY FAILURE;
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report "TIMEOUT" severity FAILURE;
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END IF;
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end if;
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-- BREAK ON EXIT (0xB8000000)
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-- BREAK ON EXIT (0xB8000000)
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IF compare(imem_i.dat_i, "10111000000000000000000000000000") = '1' THEN
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if compare(imem_i.dat_i, "10111000000000000000000000000000") = '1' then
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-- Make sure the simulator finishes when an error is encountered.
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-- Make sure the simulator finishes when an error is encountered.
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-- For modelsim: see menu Simulate -> Runtime options -> Assertions
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-- For modelsim: see menu Simulate -> Runtime options -> Assertions
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REPORT "FINISHED" SEVERITY FAILURE;
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report "FINISHED" severity FAILURE;
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END IF;
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end if;
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END PROCESS;
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end process;
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-- Character device
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-- Character device
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wb_stdio_slave: PROCESS(sys_clk_i)
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wb_stdio_slave: process(sys_clk_i)
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VARIABLE s : line;
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variable s : line;
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VARIABLE byte : std_logic_vector(7 DOWNTO 0);
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variable byte : std_logic_vector(7 downto 0);
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VARIABLE char : character;
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variable char : character;
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BEGIN
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begin
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IF rising_edge(sys_clk_i) THEN
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if rising_edge(sys_clk_i) then
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IF (wb_o.stb_o AND wb_o.cyc_o AND compare(wb_o.adr_o, std_out_adr)) = '1' THEN
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if (wb_o.stb_o and wb_o.cyc_o and compare(wb_o.adr_o, std_out_adr)) = '1' then
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IF wb_o.we_o = '1' AND std_out_ack = '0' THEN
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if wb_o.we_o = '1' and std_out_ack = '0' then
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-- WRITE STDOUT
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-- WRITE STDOUT
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std_out_ack <= '1';
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std_out_ack <= '1';
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CASE wb_o.sel_o IS
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case wb_o.sel_o is
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WHEN "0001" => byte := wb_o.dat_o( 7 DOWNTO 0);
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when "0001" => byte := wb_o.dat_o( 7 downto 0);
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WHEN "0010" => byte := wb_o.dat_o(15 DOWNTO 8);
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when "0010" => byte := wb_o.dat_o(15 downto 8);
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WHEN "0100" => byte := wb_o.dat_o(23 DOWNTO 16);
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when "0100" => byte := wb_o.dat_o(23 downto 16);
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WHEN "1000" => byte := wb_o.dat_o(31 DOWNTO 24);
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when "1000" => byte := wb_o.dat_o(31 downto 24);
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WHEN OTHERS => NULL;
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when others => null;
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END CASE;
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end case;
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char := character'val(my_conv_integer(byte));
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char := character'val(my_conv_integer(byte));
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IF byte = X"0D" THEN
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if byte = X"0D" then
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-- Ignore character 13
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-- Ignore character 13
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ELSIF byte = X"0A" THEN
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elsif byte = X"0A" then
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-- Writeline on character 10 (newline)
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-- Writeline on character 10 (newline)
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writeline(output, s);
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writeline(output, s);
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ELSE
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else
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-- Write to buffer
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-- Write to buffer
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write(s, char);
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write(s, char);
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END IF;
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end if;
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ELSIF std_out_ack = '0' THEN
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elsif std_out_ack = '0' then
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std_out_ack <= '1';
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std_out_ack <= '1';
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END IF;
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end if;
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ELSE
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else
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std_out_ack <= '0';
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std_out_ack <= '0';
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END IF;
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end if;
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END IF;
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end if;
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END PROCESS;
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end process;
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wb_i.clk_i <= sys_clk_i;
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wb_i.clk_i <= sys_clk_i;
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wb_i.rst_i <= sys_rst_i;
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wb_i.rst_i <= sys_rst_i;
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wb_i.int_i <= sys_int_i;
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wb_i.int_i <= sys_int_i;
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dmem_ena <= wb_o.stb_o AND wb_o.cyc_o AND NOT compare(wb_o.adr_o, std_out_adr);
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dmem_ena <= wb_o.stb_o and wb_o.cyc_o and not compare(wb_o.adr_o, std_out_adr);
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PROCESS(wb_o.stb_o, wb_o.cyc_o, std_out_ack, wb_o.adr_o)
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process(wb_o.stb_o, wb_o.cyc_o, std_out_ack, wb_o.adr_o)
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BEGIN
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begin
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IF NOT compare(wb_o.adr_o, std_out_adr) = '1' THEN
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if not compare(wb_o.adr_o, std_out_adr) = '1' then
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wb_i.ack_i <= wb_o.stb_o AND wb_o.cyc_o AFTER 2 ns;
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wb_i.ack_i <= wb_o.stb_o and wb_o.cyc_o after 2 ns;
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ELSE
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else
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wb_i.ack_i <= std_out_ack AFTER 22 ns;
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wb_i.ack_i <= std_out_ack after 22 ns;
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END IF;
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end if;
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END PROCESS;
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end process;
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imem : sram GENERIC MAP
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imem : sram generic map
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(
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(
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WIDTH => CFG_IMEM_WIDTH,
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WIDTH => CFG_IMEM_WIDTH,
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SIZE => rom_size - 2
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SIZE => rom_size - 2
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)
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)
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PORT MAP
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port map
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(
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(
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dat_o => imem_i.dat_i,
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dat_o => imem_i.dat_i,
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dat_i => "00000000000000000000000000000000",
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dat_i => "00000000000000000000000000000000",
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adr_i => imem_o.adr_o(rom_size - 1 DOWNTO 2),
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adr_i => imem_o.adr_o(rom_size - 1 downto 2),
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wre_i => '0',
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wre_i => '0',
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ena_i => imem_o.ena_o,
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ena_i => imem_o.ena_o,
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clk_i => sys_clk_i
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clk_i => sys_clk_i
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);
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);
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dmem_sel <= wb_o.sel_o WHEN wb_o.we_o = '1' ELSE (OTHERS => '0');
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dmem_sel <= wb_o.sel_o when wb_o.we_o = '1' else (others => '0');
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wb_i.dat_i <= X"61616161" WHEN std_out_ack = '1' ELSE dmem_dat;
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wb_i.dat_i <= X"61616161" when std_out_ack = '1' else dmem_dat;
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dmem : sram_4en GENERIC MAP
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dmem : sram_4en generic map
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(
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(
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WIDTH => CFG_DMEM_WIDTH,
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WIDTH => CFG_DMEM_WIDTH,
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SIZE => ram_size - 2
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SIZE => ram_size - 2
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)
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)
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PORT MAP
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port map
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(
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(
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dat_o => dmem_dat,
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dat_o => dmem_dat,
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dat_i => wb_o.dat_o,
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dat_i => wb_o.dat_o,
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adr_i => wb_o.adr_o(ram_size - 1 DOWNTO 2),
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adr_i => wb_o.adr_o(ram_size - 1 downto 2),
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wre_i => dmem_sel,
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wre_i => dmem_sel,
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ena_i => dmem_ena,
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ena_i => dmem_ena,
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clk_i => sys_clk_i
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clk_i => sys_clk_i
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);
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);
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core_wb0 : core_wb PORT MAP
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core_wb0 : core_wb port map
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(
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(
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imem_o => imem_o,
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imem_o => imem_o,
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wb_o => wb_o,
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wb_o => wb_o,
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imem_i => imem_i,
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imem_i => imem_i,
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wb_i => wb_i
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wb_i => wb_i
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);
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);
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END arch;
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end arch;
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No newline at end of file
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No newline at end of file
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