| Line 11... |
Line 11... |
-- of the components
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-- of the components
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--
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--
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--
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--
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.ALL;
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use ieee.std_logic_unsigned.all;
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|
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LIBRARY mblite;
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library mblite;
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USE mblite.config_Pkg.ALL;
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use mblite.config_Pkg.all;
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USE mblite.std_Pkg.ALL;
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use mblite.std_Pkg.all;
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PACKAGE core_Pkg IS
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package core_Pkg is
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constant C_8_ZEROS : std_logic_vector ( 7 downto 0) := (others => '0');
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constant C_16_ZEROS : std_logic_vector (15 downto 0) := (others => '0');
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constant C_24_ZEROS : std_logic_vector (23 downto 0) := (others => '0');
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constant C_32_ZEROS : std_logic_vector (31 downto 0) := (others => '0');
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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-- TYPES USED IN MB-LITE
|
-- TYPES USED IN MB-LITE
|
----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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TYPE alu_operation IS (ALU_ADD, ALU_OR, ALU_AND, ALU_XOR, ALU_SHIFT, ALU_SEXT8, ALU_SEXT16, ALU_MUL, ALU_BS);
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type alu_operation is (ALU_ADD, ALU_OR, ALU_AND, ALU_XOR, ALU_SHIFT, ALU_SEXT8, ALU_SEXT16, ALU_MUL, ALU_BS);
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TYPE src_type_a IS (ALU_SRC_REGA, ALU_SRC_NOT_REGA, ALU_SRC_PC, ALU_SRC_ZERO);
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type src_type_a is (ALU_SRC_REGA, ALU_SRC_NOT_REGA, ALU_SRC_PC, ALU_SRC_ZERO);
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TYPE src_type_b IS (ALU_SRC_REGB, ALU_SRC_NOT_REGB, ALU_SRC_IMM, ALU_SRC_NOT_IMM);
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type src_type_b is (ALU_SRC_REGB, ALU_SRC_NOT_REGB, ALU_SRC_IMM, ALU_SRC_NOT_IMM);
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TYPE carry_type IS (CARRY_ZERO, CARRY_ONE, CARRY_ALU, CARRY_ARITH);
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type carry_type is (CARRY_ZERO, CARRY_ONE, CARRY_ALU, CARRY_ARITH);
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TYPE carry_keep_type IS (CARRY_NOT_KEEP, CARRY_KEEP);
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type carry_keep_type is (CARRY_NOT_KEEP, CARRY_KEEP);
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TYPE branch_condition IS (NOP, BNC, BEQ, BNE, BLT, BLE, BGT, BGE);
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type branch_condition is (NOP, BNC, BEQ, BNE, BLT, BLE, BGT, BGE);
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TYPE transfer_size IS (WORD, HALFWORD, BYTE);
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type transfer_size is (WORD, HALFWORD, BYTE);
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TYPE ctrl_execution IS RECORD
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type ctrl_execution is record
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alu_op : alu_operation;
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alu_op : alu_operation;
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alu_src_a : src_type_a;
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alu_src_a : src_type_a;
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alu_src_b : src_type_b;
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alu_src_b : src_type_b;
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operation : std_logic;
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operation : std_logic;
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carry : carry_type;
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carry : carry_type;
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carry_keep : carry_keep_type;
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carry_keep : carry_keep_type;
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branch_cond : branch_condition;
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branch_cond : branch_condition;
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delay : std_logic;
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delay : std_logic;
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END RECORD;
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end record;
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TYPE ctrl_memory IS RECORD
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type ctrl_memory is record
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mem_write : std_logic;
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mem_write : std_logic;
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mem_read : std_logic;
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mem_read : std_logic;
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transfer_size : transfer_size;
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transfer_size : transfer_size;
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END RECORD;
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end record;
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TYPE ctrl_memory_writeback_type IS RECORD
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type ctrl_memory_writeback_type is record
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mem_read : std_logic;
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mem_read : std_logic;
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transfer_size : transfer_size;
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transfer_size : transfer_size;
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END RECORD;
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end record;
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TYPE forward_type IS RECORD
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type forward_type is record
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reg_d : std_logic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
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reg_d : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
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reg_write : std_logic;
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reg_write : std_logic;
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END RECORD;
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end record;
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TYPE imem_in_type IS RECORD
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type imem_in_type is record
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dat_i : std_logic_vector(CFG_IMEM_WIDTH - 1 DOWNTO 0);
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dat_i : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
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END RECORD;
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end record;
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TYPE imem_out_type IS RECORD
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type imem_out_type is record
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adr_o : std_logic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
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adr_o : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
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ena_o : std_logic;
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ena_o : std_logic;
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END RECORD;
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end record;
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TYPE fetch_in_type IS RECORD
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type fetch_in_type is record
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hazard : std_logic;
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hazard : std_logic;
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branch : std_logic;
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branch : std_logic;
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branch_target : std_logic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
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branch_target : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
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END RECORD;
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end record;
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TYPE fetch_out_type IS RECORD
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type fetch_out_type is record
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program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
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program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
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END RECORD;
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end record;
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TYPE gprf_out_type IS RECORD
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type gprf_out_type is record
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dat_a_o : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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dat_a_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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dat_b_o : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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dat_b_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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dat_d_o : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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dat_d_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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END RECORD;
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end record;
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TYPE decode_in_type IS RECORD
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type decode_in_type is record
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program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
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program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
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instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 DOWNTO 0);
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instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
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ctrl_wb : forward_type;
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ctrl_wrb : forward_type;
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ctrl_mem_wb : ctrl_memory_writeback_type;
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ctrl_mem_wrb : ctrl_memory_writeback_type;
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mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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interrupt : std_logic;
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interrupt : std_logic;
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flush_id : std_logic;
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flush_id : std_logic;
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END RECORD;
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end record;
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TYPE decode_out_type IS RECORD
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type decode_out_type is record
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reg_a : std_logic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
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reg_a : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
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reg_b : std_logic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
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reg_b : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
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imm : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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imm : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
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program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
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hazard : std_logic;
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hazard : std_logic;
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ctrl_ex : ctrl_execution;
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ctrl_ex : ctrl_execution;
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ctrl_mem : ctrl_memory;
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ctrl_mem : ctrl_memory;
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ctrl_wb : forward_type;
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ctrl_wrb : forward_type;
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fwd_dec_result : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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fwd_dec_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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fwd_dec : forward_type;
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fwd_dec : forward_type;
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END RECORD;
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end record;
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TYPE gprf_in_type IS RECORD
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type gprf_in_type is record
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adr_a_i : std_logic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
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adr_a_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
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adr_b_i : std_logic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
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adr_b_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
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adr_d_i : std_logic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
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adr_d_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
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dat_w_i : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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dat_w_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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adr_w_i : std_logic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
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adr_w_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
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wre_i : std_logic;
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wre_i : std_logic;
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END RECORD;
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end record;
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TYPE execute_out_type IS RECORD
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type execute_out_type is record
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alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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branch : std_logic;
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branch : std_logic;
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program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
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program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
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flush_id : std_logic;
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flush_id : std_logic;
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ctrl_mem : ctrl_memory;
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ctrl_mem : ctrl_memory;
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ctrl_wb : forward_type;
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ctrl_wrb : forward_type;
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END RECORD;
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end record;
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TYPE execute_in_type IS RECORD
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type execute_in_type is record
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reg_a : std_logic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
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reg_a : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
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dat_a : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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dat_a : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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reg_b : std_logic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
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reg_b : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
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dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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imm : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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imm : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
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program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
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fwd_dec : forward_type;
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fwd_dec : forward_type;
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fwd_dec_result : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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fwd_dec_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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fwd_mem : forward_type;
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fwd_mem : forward_type;
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ctrl_ex : ctrl_execution;
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ctrl_ex : ctrl_execution;
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ctrl_mem : ctrl_memory;
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ctrl_mem : ctrl_memory;
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ctrl_wb : forward_type;
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ctrl_wrb : forward_type;
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ctrl_mem_wb : ctrl_memory_writeback_type;
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ctrl_mem_wrb : ctrl_memory_writeback_type;
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mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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END RECORD;
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end record;
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TYPE mem_in_type IS RECORD
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type mem_in_type is record
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dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
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program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
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branch : std_logic;
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branch : std_logic;
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ctrl_mem : ctrl_memory;
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ctrl_mem : ctrl_memory;
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ctrl_wb : forward_type;
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ctrl_wrb : forward_type;
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END RECORD;
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end record;
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TYPE mem_out_type IS RECORD
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type mem_out_type is record
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alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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ctrl_wb : forward_type;
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ctrl_wrb : forward_type;
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ctrl_mem_wb : ctrl_memory_writeback_type;
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ctrl_mem_wrb : ctrl_memory_writeback_type;
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END RECORD;
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end record;
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TYPE dmem_in_type IS RECORD
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type dmem_in_type is record
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dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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ena_i : std_logic;
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ena_i : std_logic;
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END RECORD;
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end record;
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TYPE dmem_out_type IS RECORD
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type dmem_out_type is record
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dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0);
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adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
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sel_o : std_logic_vector(3 DOWNTO 0);
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sel_o : std_logic_vector(3 downto 0);
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we_o : std_logic;
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we_o : std_logic;
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ena_o : std_logic;
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ena_o : std_logic;
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END RECORD;
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end record;
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TYPE dmem_in_array_type IS ARRAY(NATURAL RANGE <>) OF dmem_in_type;
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type dmem_in_array_type is array(natural range <>) of dmem_in_type;
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TYPE dmem_out_array_type IS ARRAY(NATURAL RANGE <>) OF dmem_out_type;
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type dmem_out_array_type is array(natural range <>) of dmem_out_type;
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-- WB-master inputs from the wb-slaves
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-- WB-master inputs from the wb-slaves
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TYPE wb_mst_in_type IS RECORD
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type wb_mst_in_type is record
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clk_i : std_logic; -- master clock input
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clk_i : std_logic; -- master clock input
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rst_i : std_logic; -- synchronous active high reset
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rst_i : std_logic; -- synchronous active high reset
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dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0); -- databus input
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dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- databus input
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ack_i : std_logic; -- buscycle acknowledge input
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ack_i : std_logic; -- buscycle acknowledge input
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int_i : std_logic; -- interrupt request input
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int_i : std_logic; -- interrupt request input
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END RECORD;
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end record;
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|
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-- WB-master outputs to the wb-slaves
|
-- WB-master outputs to the wb-slaves
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TYPE wb_mst_out_type IS RECORD
|
type wb_mst_out_type is record
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adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0); -- address bits
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adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0); -- address bits
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dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0); -- databus output
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dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- databus output
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we_o : std_logic; -- write enable output
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we_o : std_logic; -- write enable output
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stb_o : std_logic; -- strobe signals
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stb_o : std_logic; -- strobe signals
|
sel_o : std_logic_vector(3 DOWNTO 0); -- select output array
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sel_o : std_logic_vector(3 downto 0); -- select output array
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cyc_o : std_logic; -- valid BUS cycle output
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cyc_o : std_logic; -- valid BUS cycle output
|
END RECORD;
|
end record;
|
|
|
-- WB-slave inputs, from the WB-master
|
-- WB-slave inputs, from the WB-master
|
TYPE wb_slv_in_type IS RECORD
|
type wb_slv_in_type is record
|
clk_i : std_logic; -- master clock input
|
clk_i : std_logic; -- master clock input
|
rst_i : std_logic; -- synchronous active high reset
|
rst_i : std_logic; -- synchronous active high reset
|
adr_i : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0); -- address bits
|
adr_i : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0); -- address bits
|
dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0); -- Databus input
|
dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- Databus input
|
we_i : std_logic; -- Write enable input
|
we_i : std_logic; -- Write enable input
|
stb_i : std_logic; -- strobe signals / core select signal
|
stb_i : std_logic; -- strobe signals / core select signal
|
sel_i : std_logic_vector(3 DOWNTO 0); -- select output array
|
sel_i : std_logic_vector(3 downto 0); -- select output array
|
cyc_i : std_logic; -- valid BUS cycle input
|
cyc_i : std_logic; -- valid BUS cycle input
|
END RECORD;
|
end record;
|
|
|
-- WB-slave outputs to the WB-master
|
-- WB-slave outputs to the WB-master
|
TYPE wb_slv_out_type IS RECORD
|
type wb_slv_out_type is record
|
dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0); -- Databus output
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dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- Databus output
|
ack_o : std_logic; -- Bus cycle acknowledge output
|
ack_o : std_logic; -- Bus cycle acknowledge output
|
int_o : std_logic; -- interrupt request output
|
int_o : std_logic; -- interrupt request output
|
END RECORD;
|
end record;
|
|
|
----------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------
|
-- COMPONENTS USED IN MB-LITE
|
-- COMPONENTS USED IN MB-LITE
|
----------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------
|
|
|
COMPONENT core GENERIC
|
component core
|
(
|
generic (
|
G_INTERRUPT : boolean := CFG_INTERRUPT;
|
G_INTERRUPT : boolean := CFG_INTERRUPT;
|
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
|
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
|
G_USE_BARREL : boolean := CFG_USE_BARREL;
|
G_USE_BARREL : boolean := CFG_USE_BARREL;
|
G_DEBUG : boolean := CFG_DEBUG
|
G_DEBUG : boolean := CFG_DEBUG
|
);
|
);
|
PORT
|
port (
|
(
|
imem_o : out imem_out_type;
|
imem_o : OUT imem_out_type;
|
dmem_o : out dmem_out_type;
|
dmem_o : OUT dmem_out_type;
|
imem_i : in imem_in_type;
|
imem_i : IN imem_in_type;
|
dmem_i : in dmem_in_type;
|
dmem_i : IN dmem_in_type;
|
int_i : in std_logic;
|
int_i : IN std_logic;
|
rst_i : in std_logic;
|
rst_i : IN std_logic;
|
clk_i : in std_logic
|
clk_i : IN std_logic
|
|
);
|
);
|
END COMPONENT;
|
end component;
|
|
|
COMPONENT core_wb GENERIC
|
component core_wb
|
(
|
generic (
|
G_INTERRUPT : boolean := CFG_INTERRUPT;
|
G_INTERRUPT : boolean := CFG_INTERRUPT;
|
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
|
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
|
G_USE_BARREL : boolean := CFG_USE_BARREL;
|
G_USE_BARREL : boolean := CFG_USE_BARREL;
|
G_DEBUG : boolean := CFG_DEBUG
|
G_DEBUG : boolean := CFG_DEBUG
|
);
|
);
|
PORT
|
port (
|
(
|
imem_o : out imem_out_type;
|
imem_o : OUT imem_out_type;
|
wb_o : out wb_mst_out_type;
|
wb_o : OUT wb_mst_out_type;
|
imem_i : in imem_in_type;
|
imem_i : IN imem_in_type;
|
wb_i : in wb_mst_in_type
|
wb_i : IN wb_mst_in_type
|
);
|
);
|
end component;
|
END COMPONENT;
|
|
|
component core_wb_adapter
|
COMPONENT core_wb_adapter PORT
|
port (
|
(
|
dmem_i : out dmem_in_type;
|
dmem_i : OUT dmem_in_type;
|
wb_o : out wb_mst_out_type;
|
wb_o : OUT wb_mst_out_type;
|
dmem_o : in dmem_out_type;
|
dmem_o : IN dmem_out_type;
|
wb_i : in wb_mst_in_type
|
wb_i : IN wb_mst_in_type
|
);
|
);
|
end component;
|
END COMPONENT;
|
|
|
component core_wb_async_adapter
|
COMPONENT core_wb_async_adapter PORT
|
port (
|
(
|
dmem_i : out dmem_in_type;
|
dmem_i : OUT dmem_in_type;
|
wb_o : out wb_mst_out_type;
|
wb_o : OUT wb_mst_out_type;
|
dmem_o : in dmem_out_type;
|
dmem_o : IN dmem_out_type;
|
wb_i : in wb_mst_in_type
|
wb_i : IN wb_mst_in_type
|
);
|
);
|
end component;
|
END COMPONENT;
|
|
|
component fetch
|
COMPONENT fetch PORT
|
port (
|
(
|
fetch_o : out fetch_out_type;
|
fetch_o : OUT fetch_out_type;
|
imem_o : out imem_out_type;
|
imem_o : OUT imem_out_type;
|
fetch_i : in fetch_in_type;
|
fetch_i : IN fetch_in_type;
|
rst_i : in std_logic;
|
rst_i : IN std_logic;
|
ena_i : in std_logic;
|
ena_i : IN std_logic;
|
clk_i : in std_logic
|
clk_i : IN std_logic
|
|
);
|
);
|
END COMPONENT;
|
end component;
|
|
|
COMPONENT decode GENERIC
|
component decode
|
(
|
generic (
|
G_INTERRUPT : boolean := CFG_INTERRUPT;
|
G_INTERRUPT : boolean := CFG_INTERRUPT;
|
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
|
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
|
G_USE_BARREL : boolean := CFG_USE_BARREL;
|
G_USE_BARREL : boolean := CFG_USE_BARREL;
|
G_DEBUG : boolean := CFG_DEBUG
|
G_DEBUG : boolean := CFG_DEBUG
|
);
|
);
|
PORT
|
port (
|
(
|
decode_o : out decode_out_type;
|
decode_o : OUT decode_out_type;
|
gprf_o : out gprf_out_type;
|
gprf_o : OUT gprf_out_type;
|
decode_i : in decode_in_type;
|
decode_i : IN decode_in_type;
|
ena_i : in std_logic;
|
ena_i : IN std_logic;
|
rst_i : in std_logic;
|
rst_i : IN std_logic;
|
clk_i : in std_logic
|
clk_i : IN std_logic
|
);
|
);
|
end component;
|
END COMPONENT;
|
|
|
component gprf
|
COMPONENT gprf PORT
|
port (
|
(
|
gprf_o : out gprf_out_type;
|
gprf_o : OUT gprf_out_type;
|
gprf_i : in gprf_in_type;
|
gprf_i : IN gprf_in_type;
|
ena_i : in std_logic;
|
ena_i : IN std_logic;
|
clk_i : in std_logic
|
clk_i : IN std_logic
|
|
);
|
);
|
END COMPONENT;
|
end component;
|
|
|
COMPONENT execute GENERIC
|
component execute
|
(
|
generic (
|
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
|
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
|
G_USE_BARREL : boolean := CFG_USE_BARREL
|
G_USE_BARREL : boolean := CFG_USE_BARREL
|
);
|
);
|
PORT
|
port (
|
(
|
exec_o : out execute_out_type;
|
exec_o : OUT execute_out_type;
|
exec_i : in execute_in_type;
|
exec_i : IN execute_in_type;
|
ena_i : in std_logic;
|
ena_i : IN std_logic;
|
rst_i : in std_logic;
|
rst_i : IN std_logic;
|
clk_i : in std_logic
|
clk_i : IN std_logic
|
);
|
);
|
end component;
|
END COMPONENT;
|
|
|
component mem
|
COMPONENT mem PORT
|
port (
|
(
|
mem_o : out mem_out_type;
|
mem_o : OUT mem_out_type;
|
dmem_o : out dmem_out_type;
|
dmem_o : OUT dmem_out_type;
|
mem_i : in mem_in_type;
|
mem_i : IN mem_in_type;
|
ena_i : in std_logic;
|
ena_i : IN std_logic;
|
rst_i : in std_logic;
|
rst_i : IN std_logic;
|
clk_i : in std_logic
|
clk_i : IN std_logic
|
|
);
|
);
|
END COMPONENT;
|
end component;
|
|
|
COMPONENT core_address_decoder GENERIC
|
component core_address_decoder
|
(
|
generic (
|
G_NUM_SLAVES : positive := CFG_NUM_SLAVES
|
G_NUM_SLAVES : positive := CFG_NUM_SLAVES
|
);
|
);
|
PORT
|
port (
|
(
|
m_dmem_i : out dmem_in_type;
|
m_dmem_i : OUT dmem_in_type;
|
s_dmem_o : out dmem_out_array_type;
|
s_dmem_o : OUT dmem_out_array_type;
|
m_dmem_o : in dmem_out_type;
|
m_dmem_o : IN dmem_out_type;
|
s_dmem_i : in dmem_in_array_type;
|
s_dmem_i : IN dmem_in_array_type;
|
clk_i : in std_logic
|
clk_i : IN std_logic
|
|
);
|
);
|
END COMPONENT;
|
end component;
|
----------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------
|
-- FUNCTIONS USED IN MB-LITE
|
-- FUNCTIONS USED IN MB-LITE
|
----------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------
|
|
|
FUNCTION select_register_data(reg_dat, reg, wb_dat : std_logic_vector; write : std_logic) RETURN std_logic_vector;
|
function select_register_data (reg_dat, reg, wb_dat : std_logic_vector; write : std_logic) return std_logic_vector;
|
FUNCTION forward_condition(reg_write : std_logic; reg_a, reg_d : std_logic_vector) RETURN std_logic;
|
function forward_condition (reg_write : std_logic; reg_a, reg_d : std_logic_vector) return std_logic;
|
FUNCTION align_mem_load(data : std_logic_vector; size : transfer_size; address : std_logic_vector) RETURN std_logic_vector;
|
function align_mem_load (data : std_logic_vector; size : transfer_size; address : std_logic_vector) return std_logic_vector;
|
FUNCTION align_mem_store(data : std_logic_vector; size : transfer_size) RETURN std_logic_vector;
|
function align_mem_store (data : std_logic_vector; size : transfer_size) return std_logic_vector;
|
FUNCTION decode_mem_store(address : std_logic_vector(1 DOWNTO 0); size : transfer_size) RETURN std_logic_vector;
|
function decode_mem_store (address : std_logic_vector(1 downto 0); size : transfer_size) return std_logic_vector;
|
|
|
END core_Pkg;
|
end core_Pkg;
|
|
|
PACKAGE BODY core_Pkg IS
|
package body core_Pkg is
|
|
|
-- This function select the register value:
|
-- This function select the register value:
|
-- A) zero
|
-- A) zero
|
-- B) bypass value read from register file
|
-- B) bypass value read from register file
|
-- C) value from register file
|
-- C) value from register file
|
FUNCTION select_register_data(reg_dat, reg, wb_dat : std_logic_vector; write : std_logic) RETURN std_logic_vector IS
|
function select_register_data (reg_dat, reg, wb_dat : std_logic_vector; write : std_logic) return std_logic_vector is
|
VARIABLE tmp : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
|
variable tmp : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
|
BEGIN
|
begin
|
IF CFG_REG_FORCE_ZERO = true AND is_zero(reg) = '1' THEN
|
if CFG_REG_FORCE_ZERO = true and is_zero(reg) = '1' then
|
tmp := (OTHERS => '0');
|
tmp := (others => '0');
|
ELSIF CFG_REG_FWD_WB = true AND write = '1' THEN
|
elsif CFG_REG_FWD_WRB = true and write = '1' then
|
tmp := wb_dat;
|
tmp := wb_dat;
|
ELSE
|
else
|
tmp := reg_dat;
|
tmp := reg_dat;
|
END IF;
|
end if;
|
RETURN tmp;
|
return tmp;
|
END select_register_data;
|
end select_register_data;
|
|
|
-- This function checks if a forwarding condition is met. The condition is met of register A and D match
|
-- This function checks if a forwarding condition is met. The condition is met of register A and D match
|
-- and the signal needs to be written back to the register file.
|
-- and the signal needs to be written back to the register file.
|
FUNCTION forward_condition(reg_write : std_logic; reg_a, reg_d : std_logic_vector ) RETURN std_logic IS
|
function forward_condition (reg_write : std_logic; reg_a, reg_d : std_logic_vector ) return std_logic is
|
BEGIN
|
begin
|
RETURN reg_write AND compare(reg_a, reg_d);
|
return reg_write and compare(reg_a, reg_d);
|
END forward_condition;
|
end forward_condition;
|
|
|
-- This function aligns the memory load operation. The load byte-order is defined here.
|
-- This function aligns the memory load operation (Big endian decoding).
|
FUNCTION align_mem_load(data : std_logic_vector; size : transfer_size; address : std_logic_vector ) RETURN std_logic_vector IS
|
function align_mem_load (data : std_logic_vector; size : transfer_size; address : std_logic_vector ) return std_logic_vector is
|
BEGIN
|
begin
|
IF CFG_BYTE_ORDER = false THEN
|
case size is
|
-- Little endian decoding
|
when byte =>
|
CASE size IS
|
case address(1 downto 0) is
|
WHEN byte =>
|
when "00" => return C_24_ZEROS & data(31 downto 24);
|
CASE address(1 DOWNTO 0) IS
|
when "01" => return C_24_ZEROS & data(23 downto 16);
|
WHEN "00" => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/4 - 1 DOWNTO 0);
|
when "10" => return C_24_ZEROS & data(15 downto 8);
|
WHEN "01" => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO CFG_DMEM_WIDTH/4);
|
when "11" => return C_24_ZEROS & data( 7 downto 0);
|
WHEN "10" => RETURN "000000000000000000000000" & data(3*CFG_DMEM_WIDTH/4 - 1 DOWNTO CFG_DMEM_WIDTH/2);
|
when others => return C_32_ZEROS;
|
WHEN "11" => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO 3*CFG_DMEM_WIDTH/4);
|
end case;
|
WHEN OTHERS => RETURN "00000000000000000000000000000000";
|
when halfword =>
|
END CASE;
|
case address(1 downto 0) is
|
WHEN halfword =>
|
when "00" => return C_16_ZEROS & data(31 downto 16);
|
CASE address(1 DOWNTO 0) IS
|
when "10" => return C_16_ZEROS & data(15 downto 0);
|
WHEN "00" => RETURN "0000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO 0);
|
when others => return C_32_ZEROS;
|
WHEN "10" => RETURN "0000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO CFG_DMEM_WIDTH/2);
|
end case;
|
WHEN OTHERS => RETURN "00000000000000000000000000000000";
|
when others =>
|
END CASE;
|
return data;
|
WHEN OTHERS =>
|
end case;
|
RETURN data;
|
end align_mem_load;
|
END CASE;
|
|
ELSE
|
-- This function repeats the operand to all positions in a memory store operation.
|
-- Big endian decoding
|
function align_mem_store (data : std_logic_vector; size : transfer_size) return std_logic_vector is
|
CASE size IS
|
begin
|
WHEN byte =>
|
case size is
|
CASE address(1 DOWNTO 0) IS
|
when byte => return data( 7 downto 0) & data( 7 downto 0) & data(7 downto 0) & data(7 downto 0);
|
WHEN "00" => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO 3*CFG_DMEM_WIDTH/4);
|
when halfword => return data(15 downto 0) & data(15 downto 0);
|
WHEN "01" => RETURN "000000000000000000000000" & data(3*CFG_DMEM_WIDTH/4 - 1 DOWNTO CFG_DMEM_WIDTH/2);
|
when others => return data;
|
WHEN "10" => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO CFG_DMEM_WIDTH/4);
|
end case;
|
WHEN "11" => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/4 - 1 DOWNTO 0);
|
end align_mem_store;
|
WHEN OTHERS => RETURN "00000000000000000000000000000000";
|
|
END CASE;
|
-- This function selects the correct bytes for memory writes (Big endian encoding).
|
WHEN halfword =>
|
function decode_mem_store (address : std_logic_vector(1 downto 0); size : transfer_size) return std_logic_vector is
|
CASE address(1 DOWNTO 0) IS
|
begin
|
WHEN "00" => RETURN "0000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO CFG_DMEM_WIDTH/2);
|
case size is
|
WHEN "10" => RETURN "0000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO 0);
|
when BYTE =>
|
WHEN OTHERS => RETURN "00000000000000000000000000000000";
|
case address is
|
END CASE;
|
when "00" => return "1000";
|
WHEN OTHERS =>
|
when "01" => return "0100";
|
RETURN data;
|
when "10" => return "0010";
|
END CASE;
|
when "11" => return "0001";
|
END IF;
|
when others => return "0000";
|
END align_mem_load;
|
end case;
|
|
when HALFWORD =>
|
-- This function repeats the operand to all positions memory store operation.
|
case address is
|
FUNCTION align_mem_store(data : std_logic_vector; size : transfer_size) RETURN std_logic_vector IS
|
|
BEGIN
|
|
CASE size IS
|
|
WHEN byte => RETURN data( 7 DOWNTO 0) & data( 7 DOWNTO 0) & data(7 DOWNTO 0) & data(7 DOWNTO 0);
|
|
WHEN halfword => RETURN data(15 DOWNTO 0) & data(15 DOWNTO 0);
|
|
WHEN OTHERS => RETURN data;
|
|
END CASE;
|
|
END align_mem_store;
|
|
|
|
-- This function selects the correct bytes for memory writes. The store byte-order (MSB / LSB) can be defined here.
|
|
FUNCTION decode_mem_store(address : std_logic_vector(1 DOWNTO 0); size : transfer_size) RETURN std_logic_vector IS
|
|
BEGIN
|
|
IF CFG_BYTE_ORDER = false THEN
|
|
-- Little endian encoding
|
|
CASE size IS
|
|
WHEN BYTE =>
|
|
CASE address IS
|
|
WHEN "00" => RETURN "0001";
|
|
WHEN "01" => RETURN "0010";
|
|
WHEN "10" => RETURN "0100";
|
|
WHEN "11" => RETURN "1000";
|
|
WHEN OTHERS => RETURN "0000";
|
|
END CASE;
|
|
WHEN HALFWORD =>
|
|
CASE address IS
|
|
WHEN "00" => RETURN "0011";
|
|
WHEN "10" => RETURN "1100";
|
|
WHEN OTHERS => RETURN "0000";
|
|
END CASE;
|
|
WHEN OTHERS =>
|
|
RETURN "1111";
|
|
END CASE;
|
|
ELSE
|
|
-- Big endian encoding
|
|
CASE size IS
|
|
WHEN BYTE =>
|
|
CASE address IS
|
|
WHEN "00" => RETURN "1000";
|
|
WHEN "01" => RETURN "0100";
|
|
WHEN "10" => RETURN "0010";
|
|
WHEN "11" => RETURN "0001";
|
|
WHEN OTHERS => RETURN "0000";
|
|
END CASE;
|
|
WHEN HALFWORD =>
|
|
CASE address IS
|
|
-- Big endian encoding
|
-- Big endian encoding
|
WHEN "10" => RETURN "0011";
|
when "10" => return "0011";
|
WHEN "00" => RETURN "1100";
|
when "00" => return "1100";
|
WHEN OTHERS => RETURN "0000";
|
when others => return "0000";
|
END CASE;
|
end case;
|
WHEN OTHERS =>
|
when others =>
|
RETURN "1111";
|
return "1111";
|
END CASE;
|
end case;
|
END IF;
|
end decode_mem_store;
|
END decode_mem_store;
|
|
|
|
END core_Pkg;
|
|
No newline at end of file
|
No newline at end of file
|
|
end core_Pkg;
|
No newline at end of file
|
No newline at end of file
|
