| Line 29... |
Line 29... |
(
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(
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m_dmem_i : OUT dmem_in_type;
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m_dmem_i : OUT dmem_in_type;
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s_dmem_o : OUT dmem_out_array_type(G_NUM_SLAVES - 1 DOWNTO 0);
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s_dmem_o : OUT dmem_out_array_type(G_NUM_SLAVES - 1 DOWNTO 0);
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m_dmem_o : IN dmem_out_type;
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m_dmem_o : IN dmem_out_type;
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s_dmem_i : IN dmem_in_array_type(G_NUM_SLAVES - 1 DOWNTO 0);
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s_dmem_i : IN dmem_in_array_type(G_NUM_SLAVES - 1 DOWNTO 0);
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clk_i : std_ulogic
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clk_i : std_logic
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);
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);
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END core_address_decoder;
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END core_address_decoder;
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|
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ARCHITECTURE arch OF core_address_decoder IS
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ARCHITECTURE arch OF core_address_decoder IS
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|
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-- Decodes the address based on the memory map. Returns "1" if 0 or 1 slave is attached.
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-- Decodes the address based on the memory map. Returns "1" if 0 or 1 slave is attached.
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FUNCTION decode(adr : std_ulogic_vector) RETURN std_ulogic_vector IS
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FUNCTION decode(adr : std_logic_vector) RETURN std_logic_vector IS
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VARIABLE result : std_ulogic_vector(G_NUM_SLAVES - 1 DOWNTO 0);
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VARIABLE result : std_logic_vector(G_NUM_SLAVES - 1 DOWNTO 0);
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BEGIN
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BEGIN
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result := (OTHERS => '1');
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result := (OTHERS => '1');
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IF G_NUM_SLAVES > 1 AND notx(adr) THEN
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IF G_NUM_SLAVES > 1 AND notx(adr) THEN
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FOR i IN G_NUM_SLAVES - 1 DOWNTO 0 LOOP
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FOR i IN G_NUM_SLAVES - 1 DOWNTO 0 LOOP
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IF (adr >= G_MEMORY_MAP(i) AND adr < G_MEMORY_MAP(i+1)) THEN
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IF (adr >= G_MEMORY_MAP(i) AND adr < G_MEMORY_MAP(i+1)) THEN
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| Line 52... |
Line 52... |
END LOOP;
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END LOOP;
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END IF;
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END IF;
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RETURN result;
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RETURN result;
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END FUNCTION;
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END FUNCTION;
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|
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FUNCTION demux(dmem_i : dmem_in_array_type; ce, r_ce : std_ulogic_vector) RETURN dmem_in_type IS
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FUNCTION demux(dmem_i : dmem_in_array_type; ce, r_ce : std_logic_vector) RETURN dmem_in_type IS
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VARIABLE dmem : dmem_in_type;
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VARIABLE dmem : dmem_in_type;
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BEGIN
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BEGIN
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dmem := dmem_i(0);
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dmem := dmem_i(0);
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IF notx(ce) THEN
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IF notx(ce) THEN
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FOR i IN G_NUM_SLAVES - 1 DOWNTO 0 LOOP
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FOR i IN G_NUM_SLAVES - 1 DOWNTO 0 LOOP
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| Line 69... |
Line 69... |
END LOOP;
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END LOOP;
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END IF;
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END IF;
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RETURN dmem;
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RETURN dmem;
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END FUNCTION;
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END FUNCTION;
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|
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SIGNAL r_ce, ce : std_ulogic_vector(G_NUM_SLAVES - 1 DOWNTO 0) := (OTHERS => '1');
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SIGNAL r_ce, ce : std_logic_vector(G_NUM_SLAVES - 1 DOWNTO 0) := (OTHERS => '1');
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|
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BEGIN
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BEGIN
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|
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ce <= decode(m_dmem_o.adr_o);
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ce <= decode(m_dmem_o.adr_o);
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m_dmem_i <= demux(s_dmem_i, ce, r_ce);
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m_dmem_i <= demux(s_dmem_i, ce, r_ce);
|
