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[/] [mblite/] [trunk/] [hw/] [core/] [core_wb_adapter.vhd] - Diff between revs 2 and 6
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Rev 6 |
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Line 31... |
);
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);
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END core_wb_adapter;
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END core_wb_adapter;
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ARCHITECTURE arch OF core_wb_adapter IS
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ARCHITECTURE arch OF core_wb_adapter IS
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SIGNAL r_cyc_o : std_ulogic;
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SIGNAL r_cyc_o : std_logic;
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SIGNAL rin_cyc_o : std_ulogic;
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SIGNAL rin_cyc_o : std_logic;
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SIGNAL r_data, rin_data : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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SIGNAL r_data, rin_data : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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SIGNAL s_wait : std_ulogic;
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SIGNAL s_wait : std_logic;
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BEGIN
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BEGIN
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-- Direct input-output connections
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-- Direct input-output connections
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wb_o.adr_o <= dmem_o.adr_o;
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wb_o.adr_o <= dmem_o.adr_o;
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