| Line 33... |
Line 33... |
PORT
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PORT
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(
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(
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decode_o : OUT decode_out_type;
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decode_o : OUT decode_out_type;
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gprf_o : OUT gprf_out_type;
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gprf_o : OUT gprf_out_type;
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decode_i : IN decode_in_type;
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decode_i : IN decode_in_type;
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ena_i : IN std_ulogic;
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ena_i : IN std_logic;
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rst_i : IN std_ulogic;
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rst_i : IN std_logic;
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clk_i : IN std_ulogic
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clk_i : IN std_logic
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);
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);
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END decode;
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END decode;
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|
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ARCHITECTURE arch OF decode IS
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ARCHITECTURE arch OF decode IS
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|
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TYPE decode_reg_type IS RECORD
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TYPE decode_reg_type IS RECORD
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instruction : std_ulogic_vector(CFG_IMEM_WIDTH - 1 DOWNTO 0);
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instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 DOWNTO 0);
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program_counter : std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
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program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
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immediate : std_ulogic_vector(15 DOWNTO 0);
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immediate : std_logic_vector(15 DOWNTO 0);
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is_immediate : std_ulogic;
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is_immediate : std_logic;
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msr_interrupt_enable : std_ulogic;
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msr_interrupt_enable : std_logic;
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interrupt : std_ulogic;
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interrupt : std_logic;
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delay_interrupt : std_ulogic;
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delay_interrupt : std_logic;
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END RECORD;
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END RECORD;
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|
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SIGNAL r, rin : decode_out_type;
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SIGNAL r, rin : decode_out_type;
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SIGNAL reg, regin : decode_reg_type;
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SIGNAL reg, regin : decode_reg_type;
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|
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SIGNAL wb_dat_d : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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SIGNAL wb_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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|
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BEGIN
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BEGIN
|
|
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decode_o.imm <= r.imm;
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decode_o.imm <= r.imm;
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|
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| Line 81... |
Line 81... |
r.ctrl_mem.transfer_size,r.ctrl_wb,
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r.ctrl_mem.transfer_size,r.ctrl_wb,
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r.fwd_dec,reg)
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r.fwd_dec,reg)
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|
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VARIABLE v : decode_out_type;
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VARIABLE v : decode_out_type;
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VARIABLE v_reg : decode_reg_type;
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VARIABLE v_reg : decode_reg_type;
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VARIABLE opcode : std_ulogic_vector(5 DOWNTO 0);
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VARIABLE opcode : std_logic_vector(5 DOWNTO 0);
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VARIABLE instruction : std_ulogic_vector(CFG_IMEM_WIDTH - 1 DOWNTO 0);
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VARIABLE instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 DOWNTO 0);
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VARIABLE program_counter : std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
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VARIABLE program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
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VARIABLE mem_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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VARIABLE mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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|
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BEGIN
|
BEGIN
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v := r;
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v := r;
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v_reg := reg;
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v_reg := reg;
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|
|
