| Line 12... |
Line 12... |
-- here. Everything is computed within a single clock-cycle
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-- here. Everything is computed within a single clock-cycle
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--
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--
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--
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--
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.ALL;
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use ieee.std_logic_unsigned.all;
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|
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LIBRARY mblite;
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library mblite;
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USE mblite.config_Pkg.ALL;
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use mblite.config_Pkg.all;
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USE mblite.core_Pkg.ALL;
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use mblite.core_Pkg.all;
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USE mblite.std_Pkg.ALL;
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use mblite.std_Pkg.all;
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|
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ENTITY execute IS GENERIC
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entity execute is generic
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(
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(
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G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
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G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
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G_USE_BARREL : boolean := CFG_USE_BARREL
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G_USE_BARREL : boolean := CFG_USE_BARREL
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);
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);
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PORT
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port
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(
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(
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exec_o : OUT execute_out_type;
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exec_o : out execute_out_type;
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exec_i : IN execute_in_type;
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exec_i : in execute_in_type;
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ena_i : IN std_logic;
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ena_i : in std_logic;
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rst_i : IN std_logic;
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rst_i : in std_logic;
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clk_i : IN std_logic
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clk_i : in std_logic
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);
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);
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END execute;
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end execute;
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ARCHITECTURE arch OF execute IS
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architecture arch of execute is
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TYPE execute_reg_type IS RECORD
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type execute_reg_type is record
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carry : std_logic;
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carry : std_logic;
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flush_ex : std_logic;
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flush_ex : std_logic;
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END RECORD;
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end record;
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SIGNAL r, rin : execute_out_type;
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signal r, rin : execute_out_type;
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SIGNAL reg, regin : execute_reg_type;
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signal reg, regin : execute_reg_type;
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BEGIN
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begin
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exec_o <= r;
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exec_o <= r;
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execute_comb: PROCESS(exec_i,exec_i.fwd_mem,exec_i.ctrl_ex,
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execute_comb: process(exec_i,exec_i.fwd_mem,exec_i.ctrl_ex,
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exec_i.ctrl_wb,exec_i.ctrl_mem,
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exec_i.ctrl_wrb,exec_i.ctrl_mem,
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exec_i.ctrl_mem.transfer_size,
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exec_i.ctrl_mem.transfer_size,
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exec_i.ctrl_mem_wb,exec_i.fwd_dec,
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exec_i.ctrl_mem_wrb,exec_i.fwd_dec,
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r,r.ctrl_mem,r.ctrl_mem.transfer_size,
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r,r.ctrl_mem,r.ctrl_mem.transfer_size,
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r.ctrl_wb,reg)
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r.ctrl_wrb,reg)
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VARIABLE v : execute_out_type;
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variable v : execute_out_type;
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VARIABLE v_reg : execute_reg_type;
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variable v_reg : execute_reg_type;
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VARIABLE alu_src_a : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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variable alu_src_a : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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VARIABLE alu_src_b : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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variable alu_src_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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VARIABLE carry : std_logic;
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variable carry : std_logic;
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VARIABLE result : std_logic_vector(CFG_DMEM_WIDTH DOWNTO 0);
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variable result : std_logic_vector(CFG_DMEM_WIDTH downto 0);
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VARIABLE result_add : std_logic_vector(CFG_DMEM_WIDTH DOWNTO 0);
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variable result_add : std_logic_vector(CFG_DMEM_WIDTH downto 0);
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VARIABLE zero : std_logic;
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variable zero : std_logic;
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VARIABLE dat_a, dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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variable dat_a, dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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VARIABLE sel_dat_a, sel_dat_b, sel_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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variable sel_dat_a, sel_dat_b, sel_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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VARIABLE mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
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BEGIN
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begin
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v := r;
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v := r;
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sel_dat_a := select_register_data(exec_i.dat_a, exec_i.reg_a, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_a));
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sel_dat_a := select_register_data(exec_i.dat_a, exec_i.reg_a, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_a));
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sel_dat_b := select_register_data(exec_i.dat_b, exec_i.reg_b, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_b));
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sel_dat_b := select_register_data(exec_i.dat_b, exec_i.reg_b, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_b));
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sel_dat_d := select_register_data(exec_i.dat_d, exec_i.ctrl_wb.reg_d, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.ctrl_wb.reg_d));
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sel_dat_d := select_register_data(exec_i.dat_d, exec_i.ctrl_wrb.reg_d, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.ctrl_wrb.reg_d));
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IF reg.flush_ex = '1' THEN
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if reg.flush_ex = '1' then
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v.ctrl_mem.mem_write := '0';
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v.ctrl_mem.mem_write := '0';
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v.ctrl_mem.mem_read := '0';
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v.ctrl_mem.mem_read := '0';
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v.ctrl_wb.reg_write := '0';
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v.ctrl_wrb.reg_write := '0';
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v.ctrl_wb.reg_d := (OTHERS => '0');
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v.ctrl_wrb.reg_d := (others => '0');
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ELSE
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else
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v.ctrl_mem := exec_i.ctrl_mem;
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v.ctrl_mem := exec_i.ctrl_mem;
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v.ctrl_wb := exec_i.ctrl_wb;
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v.ctrl_wrb := exec_i.ctrl_wrb;
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END IF;
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end if;
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IF exec_i.ctrl_mem_wb.mem_read = '1' THEN
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if exec_i.ctrl_mem_wrb.mem_read = '1' then
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mem_result := align_mem_load(exec_i.mem_result, exec_i.ctrl_mem_wb.transfer_size, exec_i.alu_result(1 DOWNTO 0));
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mem_result := align_mem_load(exec_i.mem_result, exec_i.ctrl_mem_wrb.transfer_size, exec_i.alu_result(1 downto 0));
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ELSE
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else
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mem_result := exec_i.alu_result;
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mem_result := exec_i.alu_result;
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END IF;
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end if;
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IF forward_condition(r.ctrl_wb.reg_write, r.ctrl_wb.reg_d, exec_i.reg_a) = '1' THEN
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if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_a) = '1' then
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-- Forward Execution Result to REG a
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-- Forward Execution Result to REG a
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dat_a := r.alu_result;
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dat_a := r.alu_result;
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ELSIF forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_a) = '1' THEN
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elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_a) = '1' then
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-- Forward Memory Result to REG a
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-- Forward Memory Result to REG a
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dat_a := mem_result;
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dat_a := mem_result;
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ELSE
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else
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-- DEFAULT: value of REG a
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-- DEFAULT: value of REG a
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dat_a := sel_dat_a;
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dat_a := sel_dat_a;
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END IF;
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end if;
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IF forward_condition(r.ctrl_wb.reg_write, r.ctrl_wb.reg_d, exec_i.reg_b) = '1' THEN
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if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_b) = '1' then
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-- Forward (latched) Execution Result to REG b
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-- Forward (latched) Execution Result to REG b
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dat_b := r.alu_result;
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dat_b := r.alu_result;
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ELSIF forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_b) = '1' THEN
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elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_b) = '1' then
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-- Forward Memory Result to REG b
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-- Forward Memory Result to REG b
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dat_b := mem_result;
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dat_b := mem_result;
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ELSE
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else
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-- DEFAULT: value of REG b
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-- DEFAULT: value of REG b
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dat_b := sel_dat_b;
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dat_b := sel_dat_b;
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END IF;
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end if;
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IF forward_condition(r.ctrl_wb.reg_write, r.ctrl_wb.reg_d, exec_i.ctrl_wb.reg_d) = '1' THEN
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if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
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-- Forward Execution Result to REG d
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-- Forward Execution Result to REG d
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v.dat_d := align_mem_store(r.alu_result, exec_i.ctrl_mem.transfer_size);
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v.dat_d := align_mem_store(r.alu_result, exec_i.ctrl_mem.transfer_size);
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ELSIF forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.ctrl_wb.reg_d) = '1' THEN
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elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
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-- Forward Memory Result to REG d
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-- Forward Memory Result to REG d
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v.dat_d := align_mem_store(mem_result, exec_i.ctrl_mem.transfer_size);
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v.dat_d := align_mem_store(mem_result, exec_i.ctrl_mem.transfer_size);
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ELSE
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else
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-- DEFAULT: value of REG d
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-- DEFAULT: value of REG d
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v.dat_d := align_mem_store(sel_dat_d, exec_i.ctrl_mem.transfer_size);
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v.dat_d := align_mem_store(sel_dat_d, exec_i.ctrl_mem.transfer_size);
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END IF;
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end if;
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-- Set the first operand of the ALU
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-- Set the first operand of the ALU
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CASE exec_i.ctrl_ex.alu_src_a IS
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case exec_i.ctrl_ex.alu_src_a is
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WHEN ALU_SRC_PC => alu_src_a := sign_extend(exec_i.program_counter, '0', 32);
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when ALU_SRC_PC => alu_src_a := sign_extend(exec_i.program_counter, '0', 32);
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WHEN ALU_SRC_NOT_REGA => alu_src_a := NOT dat_a;
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when ALU_SRC_NOT_REGA => alu_src_a := not dat_a;
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WHEN ALU_SRC_ZERO => alu_src_a := (OTHERS => '0');
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when ALU_SRC_ZERO => alu_src_a := (others => '0');
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WHEN OTHERS => alu_src_a := dat_a;
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when others => alu_src_a := dat_a;
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END CASE;
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end case;
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-- Set the second operand of the ALU
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-- Set the second operand of the ALU
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CASE exec_i.ctrl_ex.alu_src_b IS
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case exec_i.ctrl_ex.alu_src_b is
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WHEN ALU_SRC_IMM => alu_src_b := exec_i.imm;
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when ALU_SRC_IMM => alu_src_b := exec_i.imm;
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WHEN ALU_SRC_NOT_IMM => alu_src_b := NOT exec_i.imm;
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when ALU_SRC_NOT_IMM => alu_src_b := not exec_i.imm;
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WHEN ALU_SRC_NOT_REGB => alu_src_b := NOT dat_b;
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when ALU_SRC_NOT_REGB => alu_src_b := not dat_b;
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WHEN OTHERS => alu_src_b := dat_b;
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when others => alu_src_b := dat_b;
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END CASE;
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end case;
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-- Determine value of carry in
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-- Determine value of carry in
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CASE exec_i.ctrl_ex.carry IS
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case exec_i.ctrl_ex.carry is
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WHEN CARRY_ALU => carry := reg.carry;
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when CARRY_ALU => carry := reg.carry;
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WHEN CARRY_ONE => carry := '1';
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when CARRY_ONE => carry := '1';
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WHEN CARRY_ARITH => carry := alu_src_a(CFG_DMEM_WIDTH - 1);
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when CARRY_ARITH => carry := alu_src_a(CFG_DMEM_WIDTH - 1);
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WHEN OTHERS => carry := '0';
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when others => carry := '0';
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END CASE;
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end case;
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result_add := add(alu_src_a, alu_src_b, carry);
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result_add := add(alu_src_a, alu_src_b, carry);
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CASE exec_i.ctrl_ex.alu_op IS
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case exec_i.ctrl_ex.alu_op is
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WHEN ALU_ADD => result := result_add;
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when ALU_ADD => result := result_add;
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WHEN ALU_OR => result := '0' & (alu_src_a OR alu_src_b);
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when ALU_OR => result := '0' & (alu_src_a or alu_src_b);
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WHEN ALU_AND => result := '0' & (alu_src_a AND alu_src_b);
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when ALU_AND => result := '0' & (alu_src_a and alu_src_b);
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WHEN ALU_XOR => result := '0' & (alu_src_a XOR alu_src_b);
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when ALU_XOR => result := '0' & (alu_src_a xor alu_src_b);
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WHEN ALU_SHIFT => result := alu_src_a(0) & carry & alu_src_a(CFG_DMEM_WIDTH - 1 DOWNTO 1);
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when ALU_SHIFT => result := alu_src_a(0) & carry & alu_src_a(CFG_DMEM_WIDTH - 1 downto 1);
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WHEN ALU_SEXT8 => result := '0' & sign_extend(alu_src_a(7 DOWNTO 0), alu_src_a(7), 32);
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when ALU_SEXT8 => result := '0' & sign_extend(alu_src_a(7 downto 0), alu_src_a(7), 32);
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WHEN ALU_SEXT16 => result := '0' & sign_extend(alu_src_a(15 DOWNTO 0), alu_src_a(15), 32);
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when ALU_SEXT16 => result := '0' & sign_extend(alu_src_a(15 downto 0), alu_src_a(15), 32);
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WHEN ALU_MUL =>
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when ALU_MUL =>
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IF G_USE_HW_MUL = true THEN
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if G_USE_HW_MUL = true then
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result := '0' & multiply(alu_src_a, alu_src_b);
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result := '0' & multiply(alu_src_a, alu_src_b);
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ELSE
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else
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result := (OTHERS => '0');
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result := (others => '0');
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END IF;
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end if;
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WHEN ALU_BS =>
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when ALU_BS =>
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IF G_USE_BARREL = true THEN
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if G_USE_BARREL = true then
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result := '0' & shift(alu_src_a, alu_src_b(4 DOWNTO 0), exec_i.imm(10), exec_i.imm(9));
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result := '0' & shift(alu_src_a, alu_src_b(4 downto 0), exec_i.imm(10), exec_i.imm(9));
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ELSE
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else
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result := (OTHERS => '0');
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result := (others => '0');
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END IF;
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end if;
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WHEN OTHERS =>
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when others =>
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result := (OTHERS => '0');
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result := (others => '0');
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REPORT "Invalid ALU operation" SEVERITY FAILURE;
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report "Invalid ALU operation" severity FAILURE;
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END CASE;
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end case;
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-- Set carry register
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-- Set carry register
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IF exec_i.ctrl_ex.carry_keep = CARRY_KEEP THEN
|
if exec_i.ctrl_ex.carry_keep = CARRY_KEEP then
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v_reg.carry := reg.carry;
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v_reg.carry := reg.carry;
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ELSE
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else
|
v_reg.carry := result(CFG_DMEM_WIDTH);
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v_reg.carry := result(CFG_DMEM_WIDTH);
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END IF;
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end if;
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|
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zero := is_zero(dat_a);
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zero := is_zero(dat_a);
|
|
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-- Overwrite branch condition
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-- Overwrite branch condition
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IF reg.flush_ex = '1' THEN
|
if reg.flush_ex = '1' then
|
v.branch := '0';
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v.branch := '0';
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ELSE
|
else
|
-- Determine branch condition
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-- Determine branch condition
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CASE exec_i.ctrl_ex.branch_cond IS
|
case exec_i.ctrl_ex.branch_cond is
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WHEN BNC => v.branch := '1';
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when BNC => v.branch := '1';
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WHEN BEQ => v.branch := zero;
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when BEQ => v.branch := zero;
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WHEN BNE => v.branch := NOT zero;
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when BNE => v.branch := not zero;
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WHEN BLT => v.branch := dat_a(CFG_DMEM_WIDTH - 1);
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when BLT => v.branch := dat_a(CFG_DMEM_WIDTH - 1);
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WHEN BLE => v.branch := dat_a(CFG_DMEM_WIDTH - 1) OR zero;
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when BLE => v.branch := dat_a(CFG_DMEM_WIDTH - 1) or zero;
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WHEN BGT => v.branch := NOT (dat_a(CFG_DMEM_WIDTH - 1) OR zero);
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when BGT => v.branch := not (dat_a(CFG_DMEM_WIDTH - 1) or zero);
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WHEN BGE => v.branch := NOT dat_a(CFG_DMEM_WIDTH - 1);
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when BGE => v.branch := not dat_a(CFG_DMEM_WIDTH - 1);
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WHEN OTHERS => v.branch := '0';
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when others => v.branch := '0';
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END CASE;
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end case;
|
END IF;
|
end if;
|
|
|
-- Handle CMPU
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-- Handle CMPU
|
IF ( exec_i.ctrl_ex.operation AND NOT (alu_src_a(CFG_DMEM_WIDTH - 1) XOR alu_src_b(CFG_DMEM_WIDTH - 1))) = '1' THEN
|
if ( exec_i.ctrl_ex.operation and not (alu_src_a(CFG_DMEM_WIDTH - 1) xor alu_src_b(CFG_DMEM_WIDTH - 1))) = '1' then
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-- Set MSB
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-- Set MSB
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v.alu_result(CFG_DMEM_WIDTH - 1 DOWNTO 0) := (NOT result(CFG_DMEM_WIDTH - 1)) & result(CFG_DMEM_WIDTH - 2 DOWNTO 0);
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v.alu_result(CFG_DMEM_WIDTH - 1 downto 0) := (not result(CFG_DMEM_WIDTH - 1)) & result(CFG_DMEM_WIDTH - 2 downto 0);
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ELSE
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else
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-- Use ALU result
|
-- Use ALU result
|
v.alu_result := result(CFG_DMEM_WIDTH - 1 DOWNTO 0);
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v.alu_result := result(CFG_DMEM_WIDTH - 1 downto 0);
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END IF;
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end if;
|
|
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v.program_counter := exec_i.program_counter;
|
v.program_counter := exec_i.program_counter;
|
|
|
-- Determine flush signals
|
-- Determine flush signals
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v.flush_id := v.branch;
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v.flush_id := v.branch;
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v_reg.flush_ex := v.branch AND NOT exec_i.ctrl_ex.delay;
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v_reg.flush_ex := v.branch and not exec_i.ctrl_ex.delay;
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rin <= v;
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rin <= v;
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regin <= v_reg;
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regin <= v_reg;
|
|
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END PROCESS;
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end process;
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|
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execute_seq: PROCESS(clk_i)
|
execute_seq: process(clk_i)
|
PROCEDURE proc_execute_reset IS
|
procedure proc_execute_reset is
|
BEGIN
|
begin
|
r.alu_result <= (OTHERS => '0');
|
r.alu_result <= (others => '0');
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r.dat_d <= (OTHERS => '0');
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r.dat_d <= (others => '0');
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r.branch <= '0';
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r.branch <= '0';
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r.program_counter <= (OTHERS => '0');
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r.program_counter <= (others => '0');
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r.flush_id <= '0';
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r.flush_id <= '0';
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r.ctrl_mem.mem_write <= '0';
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r.ctrl_mem.mem_write <= '0';
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r.ctrl_mem.mem_read <= '0';
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r.ctrl_mem.mem_read <= '0';
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r.ctrl_mem.transfer_size <= WORD;
|
r.ctrl_mem.transfer_size <= WORD;
|
r.ctrl_wb.reg_d <= (OTHERS => '0');
|
r.ctrl_wrb.reg_d <= (others => '0');
|
r.ctrl_wb.reg_write <= '0';
|
r.ctrl_wrb.reg_write <= '0';
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reg.carry <= '0';
|
reg.carry <= '0';
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reg.flush_ex <= '0';
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reg.flush_ex <= '0';
|
END PROCEDURE proc_execute_reset;
|
end procedure proc_execute_reset;
|
BEGIN
|
begin
|
IF rising_edge(clk_i) THEN
|
if rising_edge(clk_i) then
|
IF rst_i = '1' THEN
|
if rst_i = '1' then
|
proc_execute_reset;
|
proc_execute_reset;
|
ELSIF ena_i = '1' THEN
|
elsif ena_i = '1' then
|
r <= rin;
|
r <= rin;
|
reg <= regin;
|
reg <= regin;
|
END IF;
|
end if;
|
END IF;
|
end if;
|
END PROCESS;
|
end process;
|
END arch;
|
end arch;
|
|
|
No newline at end of file
|
No newline at end of file
|
