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-- the register file. All outputs are registered, possibly by using
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-- the register file. All outputs are registered, possibly by using
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-- registered memory elements.
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-- registered memory elements.
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--
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--
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.ALL;
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use ieee.std_logic_unsigned.all;
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LIBRARY mblite;
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library mblite;
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USE mblite.config_Pkg.ALL;
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use mblite.config_Pkg.all;
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USE mblite.core_Pkg.ALL;
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use mblite.core_Pkg.all;
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USE mblite.std_Pkg.ALL;
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use mblite.std_Pkg.all;
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ENTITY gprf IS PORT
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entity gprf is port
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(
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(
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gprf_o : OUT gprf_out_type;
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gprf_o : out gprf_out_type;
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gprf_i : IN gprf_in_type;
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gprf_i : in gprf_in_type;
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ena_i : IN std_logic;
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ena_i : in std_logic;
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clk_i : IN std_logic
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clk_i : in std_logic
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);
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);
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END gprf;
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end gprf;
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-- This architecture is the default implementation. It
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-- This architecture is the default implementation. It
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-- consists of three dual port memories. Other
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-- consists of three dual port memories. Other
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-- architectures can be added while configurations can
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-- architectures can be added while configurations can
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-- control the implemented architecture.
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-- control the implemented architecture.
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ARCHITECTURE arch OF gprf IS
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architecture arch of gprf is
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BEGIN
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begin
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a : dsram GENERIC MAP
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a : dsram generic map
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(
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(
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WIDTH => CFG_DMEM_WIDTH,
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WIDTH => CFG_DMEM_WIDTH,
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SIZE => CFG_GPRF_SIZE
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SIZE => CFG_GPRF_SIZE
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)
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)
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PORT MAP
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port map
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(
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(
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dat_o => gprf_o.dat_a_o,
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dat_o => gprf_o.dat_a_o,
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adr_i => gprf_i.adr_a_i,
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adr_i => gprf_i.adr_a_i,
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ena_i => ena_i,
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ena_i => ena_i,
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dat_w_i => gprf_i.dat_w_i,
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dat_w_i => gprf_i.dat_w_i,
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adr_w_i => gprf_i.adr_w_i,
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adr_w_i => gprf_i.adr_w_i,
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wre_i => gprf_i.wre_i,
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wre_i => gprf_i.wre_i,
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clk_i => clk_i
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clk_i => clk_i
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);
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);
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b : dsram GENERIC MAP
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b : dsram generic map
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(
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(
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WIDTH => CFG_DMEM_WIDTH,
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WIDTH => CFG_DMEM_WIDTH,
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SIZE => CFG_GPRF_SIZE
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SIZE => CFG_GPRF_SIZE
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)
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)
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PORT MAP
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port map
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(
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(
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dat_o => gprf_o.dat_b_o,
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dat_o => gprf_o.dat_b_o,
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adr_i => gprf_i.adr_b_i,
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adr_i => gprf_i.adr_b_i,
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ena_i => ena_i,
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ena_i => ena_i,
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dat_w_i => gprf_i.dat_w_i,
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dat_w_i => gprf_i.dat_w_i,
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adr_w_i => gprf_i.adr_w_i,
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adr_w_i => gprf_i.adr_w_i,
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wre_i => gprf_i.wre_i,
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wre_i => gprf_i.wre_i,
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clk_i => clk_i
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clk_i => clk_i
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);
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);
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d : dsram GENERIC MAP
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d : dsram generic map
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(
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(
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WIDTH => CFG_DMEM_WIDTH,
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WIDTH => CFG_DMEM_WIDTH,
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SIZE => CFG_GPRF_SIZE
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SIZE => CFG_GPRF_SIZE
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)
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)
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PORT MAP
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port map
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(
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(
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dat_o => gprf_o.dat_d_o,
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dat_o => gprf_o.dat_d_o,
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adr_i => gprf_i.adr_d_i,
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adr_i => gprf_i.adr_d_i,
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ena_i => ena_i,
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ena_i => ena_i,
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dat_w_i => gprf_i.dat_w_i,
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dat_w_i => gprf_i.dat_w_i,
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adr_w_i => gprf_i.adr_w_i,
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adr_w_i => gprf_i.adr_w_i,
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wre_i => gprf_i.wre_i,
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wre_i => gprf_i.wre_i,
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clk_i => clk_i
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clk_i => clk_i
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);
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);
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END arch;
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end arch;
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No newline at end of file
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No newline at end of file
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