| Line 32... |
Line 32... |
ENTITY mem IS PORT
|
ENTITY mem IS PORT
|
(
|
(
|
mem_o : OUT mem_out_type;
|
mem_o : OUT mem_out_type;
|
dmem_o : OUT dmem_out_type;
|
dmem_o : OUT dmem_out_type;
|
mem_i : IN mem_in_type;
|
mem_i : IN mem_in_type;
|
ena_i : IN std_ulogic;
|
ena_i : IN std_logic;
|
rst_i : IN std_ulogic;
|
rst_i : IN std_logic;
|
clk_i : IN std_ulogic
|
clk_i : IN std_logic
|
);
|
);
|
END mem;
|
END mem;
|
|
|
ARCHITECTURE arch OF mem IS
|
ARCHITECTURE arch OF mem IS
|
SIGNAL r, rin : mem_out_type;
|
SIGNAL r, rin : mem_out_type;
|
SIGNAL mem_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
|
SIGNAL mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
|
BEGIN
|
BEGIN
|
-- connect pipline signals
|
-- connect pipline signals
|
mem_o.ctrl_wb <= r.ctrl_wb;
|
mem_o.ctrl_wb <= r.ctrl_wb;
|
mem_o.ctrl_mem_wb <= r.ctrl_mem_wb;
|
mem_o.ctrl_mem_wb <= r.ctrl_mem_wb;
|
mem_o.alu_result <= r.alu_result;
|
mem_o.alu_result <= r.alu_result;
|
| Line 56... |
Line 56... |
dmem_o.adr_o <= mem_i.alu_result(CFG_DMEM_SIZE - 1 DOWNTO 0);
|
dmem_o.adr_o <= mem_i.alu_result(CFG_DMEM_SIZE - 1 DOWNTO 0);
|
dmem_o.ena_o <= mem_i.ctrl_mem.mem_read OR mem_i.ctrl_mem.mem_write;
|
dmem_o.ena_o <= mem_i.ctrl_mem.mem_read OR mem_i.ctrl_mem.mem_write;
|
|
|
mem_comb: PROCESS(mem_i, mem_i.ctrl_wb, mem_i.ctrl_mem, r, r.ctrl_wb, r.ctrl_mem_wb)
|
mem_comb: PROCESS(mem_i, mem_i.ctrl_wb, mem_i.ctrl_mem, r, r.ctrl_wb, r.ctrl_mem_wb)
|
VARIABLE v : mem_out_type;
|
VARIABLE v : mem_out_type;
|
VARIABLE intermediate : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
|
VARIABLE intermediate : std_logic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
|
BEGIN
|
BEGIN
|
|
|
v := r;
|
v := r;
|
v.ctrl_wb := mem_i.ctrl_wb;
|
v.ctrl_wb := mem_i.ctrl_wb;
|
|
|
