Subversion Repositories mblite

LIBRARY ieee;

library ieee;

USE ieee.std_logic_1164.ALL;

use ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.ALL;

use ieee.std_logic_unsigned.all;

LIBRARY mblite;

library mblite;

USE mblite.std_Pkg.ALL;

use mblite.std_Pkg.all;

ENTITY dsram IS GENERIC

entity dsram is generic

PORT

port

    dat_o   : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);

    dat_o   : out std_logic_vector(WIDTH - 1 downto 0);

    adr_i   : IN std_logic_vector(SIZE - 1 DOWNTO 0);

    adr_i   : in std_logic_vector(SIZE - 1 downto 0);

    ena_i   : IN std_logic;

    ena_i   : in std_logic;

    dat_w_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);

    dat_w_i : in std_logic_vector(WIDTH - 1 downto 0);

    adr_w_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);

    adr_w_i : in std_logic_vector(SIZE - 1 downto 0);

    wre_i   : IN std_logic;

    wre_i   : in std_logic;

    clk_i   : IN std_logic

    clk_i   : in std_logic

END dsram;

end dsram;

ARCHITECTURE arch OF dsram IS

architecture arch of dsram is

    TYPE ram_type IS array(2 ** SIZE - 1 DOWNTO 0) OF std_logic_vector(WIDTH - 1 DOWNTO 0);

    type ram_type is array(2 ** SIZE - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);

    SIGNAL ram :  ram_type;

    signal ram :  ram_type;

BEGIN

begin

    PROCESS(clk_i)

    process(clk_i)

    BEGIN

    begin

        IF rising_edge(clk_i) THEN

        if rising_edge(clk_i) then

            IF ena_i = '1' THEN

            if ena_i = '1' then

                IF wre_i = '1' THEN

                if wre_i = '1' then

                END IF;

                end if;

            END IF;

            end if;

        END IF;

        end if;

    END PROCESS;

    end process;

END arch;

end arch;