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[/] [mblite/] [trunk/] [hw/] [std/] [sram.vhd] - Diff between revs 6 and 8
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--
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--
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-- Description : Single Port Synchronous Random Access Memory
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-- Description : Single Port Synchronous Random Access Memory
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--
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--
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.ALL;
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use ieee.std_logic_unsigned.all;
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LIBRARY mblite;
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library mblite;
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USE mblite.std_Pkg.ALL;
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use mblite.std_Pkg.all;
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ENTITY sram IS GENERIC
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entity sram is generic
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(
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(
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WIDTH : positive := 32;
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WIDTH : positive := 32;
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SIZE : positive := 16
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SIZE : positive := 16
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);
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);
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PORT
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port
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(
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(
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dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
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dat_o : out std_logic_vector(WIDTH - 1 downto 0);
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dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
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dat_i : in std_logic_vector(WIDTH - 1 downto 0);
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adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
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adr_i : in std_logic_vector(SIZE - 1 downto 0);
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wre_i : IN std_logic;
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wre_i : in std_logic;
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ena_i : IN std_logic;
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ena_i : in std_logic;
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clk_i : IN std_logic
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clk_i : in std_logic
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);
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);
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END sram;
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end sram;
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ARCHITECTURE arch OF sram IS
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architecture arch of sram is
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TYPE ram_type IS array(2 ** SIZE - 1 DOWNTO 0) OF std_logic_vector(WIDTH - 1 DOWNTO 0);
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type ram_type is array(2 ** SIZE - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
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SIGNAL ram : ram_type;
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signal ram : ram_type;
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BEGIN
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begin
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PROCESS(clk_i)
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process(clk_i)
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BEGIN
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begin
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IF rising_edge(clk_i) THEN
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if rising_edge(clk_i) then
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IF ena_i = '1' THEN
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if ena_i = '1' then
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IF wre_i = '1' THEN
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if wre_i = '1' then
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ram(my_conv_integer(adr_i)) <= dat_i;
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ram(my_conv_integer(adr_i)) <= dat_i;
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END IF;
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end if;
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dat_o <= ram(my_conv_integer(adr_i));
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dat_o <= ram(my_conv_integer(adr_i));
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END IF;
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end if;
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END IF;
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end if;
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END PROCESS;
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end process;
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END arch;
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end arch;
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