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-- Architecture 'arch' : Default implementation
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-- Architecture 'arch' : Default implementation
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-- Architecture 'arch2' : Alternative implementation
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-- Architecture 'arch2' : Alternative implementation
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--
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--
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.ALL;
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use ieee.std_logic_unsigned.all;
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LIBRARY mblite;
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library mblite;
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USE mblite.std_Pkg.ALL;
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use mblite.std_Pkg.all;
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ENTITY sram_4en IS GENERIC
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entity sram_4en is generic
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(
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(
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WIDTH : positive := 32;
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WIDTH : positive := 32;
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SIZE : positive := 16
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SIZE : positive := 16
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);
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);
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PORT
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port
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(
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(
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dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
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dat_o : out std_logic_vector(WIDTH - 1 downto 0);
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dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
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dat_i : in std_logic_vector(WIDTH - 1 downto 0);
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adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
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adr_i : in std_logic_vector(SIZE - 1 downto 0);
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wre_i : IN std_logic_vector(WIDTH/8 - 1 DOWNTO 0);
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wre_i : in std_logic_vector(WIDTH/8 - 1 downto 0);
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ena_i : IN std_logic;
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ena_i : in std_logic;
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clk_i : IN std_logic
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clk_i : in std_logic
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);
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);
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END sram_4en;
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end sram_4en;
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-- Although this memory is very easy to use in conjunction with Modelsims mem load, it is not
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-- Although this memory is very easy to use in conjunction with Modelsims mem load, it is not
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-- supported by many devices (although it comes straight from the library. Many devices give
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-- supported by many devices (although it comes straight from the library. Many devices give
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-- cryptic synthesization errors on this implementation, so it is not the default.
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-- cryptic synthesization errors on this implementation, so it is not the default.
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ARCHITECTURE arch2 OF sram_4en IS
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architecture arch2 of sram_4en is
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TYPE ram_type IS array(2 ** SIZE - 1 DOWNTO 0) OF std_logic_vector(WIDTH - 1 DOWNTO 0);
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type ram_type is array(2 ** SIZE - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
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TYPE sel_type IS array(WIDTH/8 - 1 DOWNTO 0) OF std_logic_vector(7 DOWNTO 0);
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type sel_type is array(WIDTH/8 - 1 downto 0) of std_logic_vector(7 downto 0);
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SIGNAL ram: ram_type;
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signal ram: ram_type;
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SIGNAL di: sel_type;
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signal di: sel_type;
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BEGIN
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begin
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PROCESS(wre_i, dat_i, adr_i)
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process(wre_i, dat_i, adr_i)
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BEGIN
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begin
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FOR i IN 0 TO WIDTH/8 - 1 LOOP
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for i in 0 to WIDTH/8 - 1 loop
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IF wre_i(i) = '1' THEN
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if wre_i(i) = '1' then
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di(i) <= dat_i((i+1)*8 - 1 DOWNTO i*8);
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di(i) <= dat_i((i+1)*8 - 1 downto i*8);
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ELSE
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else
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di(i) <= ram(my_conv_integer(adr_i))((i+1)*8 - 1 DOWNTO i*8);
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di(i) <= ram(my_conv_integer(adr_i))((i+1)*8 - 1 downto i*8);
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END IF;
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end if;
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END LOOP;
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end loop;
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END PROCESS;
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end process;
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PROCESS(clk_i)
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process(clk_i)
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BEGIN
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begin
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IF rising_edge(clk_i) THEN
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if rising_edge(clk_i) then
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IF ena_i = '1' THEN
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if ena_i = '1' then
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ram(my_conv_integer(adr_i)) <= di(3) & di(2) & di(1) & di(0);
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ram(my_conv_integer(adr_i)) <= di(3) & di(2) & di(1) & di(0);
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dat_o <= di(3) & di(2) & di(1) & di(0);
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dat_o <= di(3) & di(2) & di(1) & di(0);
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END IF;
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end if;
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END IF;
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end if;
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END PROCESS;
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end process;
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END arch2;
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end arch2;
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-- Less convenient but very general memory block with four separate write
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-- Less convenient but very general memory block with four separate write
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-- enable signals. (4x8 bit)
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-- enable signals. (4x8 bit)
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ARCHITECTURE arch OF sram_4en IS
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architecture arch of sram_4en is
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BEGIN
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begin
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mem: FOR i IN 0 TO WIDTH/8 - 1 GENERATE
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mem: for i in 0 to WIDTH/8 - 1 generate
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mem : sram GENERIC MAP
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mem : sram generic map
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(
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(
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WIDTH => 8,
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WIDTH => 8,
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SIZE => SIZE
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SIZE => SIZE
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)
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)
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PORT MAP
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port map
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(
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(
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dat_o => dat_o((i+1)*8 - 1 DOWNTO i*8),
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dat_o => dat_o((i+1)*8 - 1 downto i*8),
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dat_i => dat_i((i+1)*8 - 1 DOWNTO i*8),
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dat_i => dat_i((i+1)*8 - 1 downto i*8),
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adr_i => adr_i,
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adr_i => adr_i,
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wre_i => wre_i(i),
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wre_i => wre_i(i),
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ena_i => ena_i,
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ena_i => ena_i,
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clk_i => clk_i
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clk_i => clk_i
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);
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);
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END GENERATE;
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end generate;
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END arch;
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end arch;
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No newline at end of file
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No newline at end of file
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