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[/] [mblite/] [trunk/] [hw/] [std/] [sram_4en.vhd] - Diff between revs 5 and 6
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| Rev 5 |
Rev 6 |
| Line 26... |
Line 26... |
WIDTH : positive := 32;
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WIDTH : positive := 32;
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SIZE : positive := 16
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SIZE : positive := 16
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);
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);
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PORT
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PORT
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(
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(
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dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
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dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
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adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
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adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
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wre_i : IN std_ulogic_vector(WIDTH/8 - 1 DOWNTO 0);
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wre_i : IN std_logic_vector(WIDTH/8 - 1 DOWNTO 0);
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ena_i : IN std_ulogic;
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ena_i : IN std_logic;
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clk_i : IN std_ulogic
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clk_i : IN std_logic
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);
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);
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END sram_4en;
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END sram_4en;
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-- Although this memory is very easy to use in conjunction with Modelsims mem load, it is not
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-- Although this memory is very easy to use in conjunction with Modelsims mem load, it is not
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-- supported by many devices (although it comes straight from the library. Many devices give
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-- supported by many devices (although it comes straight from the library. Many devices give
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-- cryptic synthesization errors on this implementation, so it is not the default.
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-- cryptic synthesization errors on this implementation, so it is not the default.
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ARCHITECTURE arch2 OF sram_4en IS
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ARCHITECTURE arch2 OF sram_4en IS
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TYPE ram_type IS array(2 ** SIZE - 1 DOWNTO 0) OF std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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TYPE ram_type IS array(2 ** SIZE - 1 DOWNTO 0) OF std_logic_vector(WIDTH - 1 DOWNTO 0);
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TYPE sel_type IS array(WIDTH/8 - 1 DOWNTO 0) OF std_ulogic_vector(7 DOWNTO 0);
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TYPE sel_type IS array(WIDTH/8 - 1 DOWNTO 0) OF std_logic_vector(7 DOWNTO 0);
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SIGNAL ram: ram_type;
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SIGNAL ram: ram_type;
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SIGNAL di: sel_type;
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SIGNAL di: sel_type;
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BEGIN
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BEGIN
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PROCESS(wre_i, dat_i, adr_i)
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PROCESS(wre_i, dat_i, adr_i)
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