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--
--
--      Description        : Package with several standard components.
--      Description        : Package with several standard components.
--
--
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
 
 
LIBRARY ieee;
library ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
use ieee.numeric_std.all;
 
 
PACKAGE std_Pkg IS
PACKAGE std_Pkg IS
 
 
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
-- STANDARD COMPONENTS IN STD_PKG
-- STANDARD COMPONENTS IN STD_PKG
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
 
 
    COMPONENT sram GENERIC
    component sram generic
    (
    (
        WIDTH : positive;
        WIDTH : positive;
        SIZE  : positive
        SIZE  : positive
    );
    );
    PORT
    port
    (
    (
        dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
        dat_o : out std_logic_vector(WIDTH - 1 downto 0);
        dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
        dat_i : in std_logic_vector(WIDTH - 1 downto 0);
        adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
        adr_i : in std_logic_vector(SIZE - 1 downto 0);
        wre_i : IN std_logic;
        wre_i : in std_logic;
        ena_i : IN std_logic;
        ena_i : in std_logic;
        clk_i : IN std_logic
        clk_i : in std_logic
    );
    );
    END COMPONENT;
    end component;
 
 
    COMPONENT sram_4en GENERIC
    component sram_4en generic
    (
    (
        WIDTH : positive;
        WIDTH : positive;
        SIZE  : positive
        SIZE  : positive
    );
    );
    PORT
    port
    (
    (
        dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
        dat_o : out std_logic_vector(WIDTH - 1 downto 0);
        dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
        dat_i : in std_logic_vector(WIDTH - 1 downto 0);
        adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
        adr_i : in std_logic_vector(SIZE - 1 downto 0);
        wre_i : IN std_logic_vector(3 DOWNTO 0);
        wre_i : in std_logic_vector(3 downto 0);
        ena_i : IN std_logic;
        ena_i : in std_logic;
        clk_i : IN std_logic
        clk_i : in std_logic
    );
    );
    END COMPONENT;
    end component;
 
 
    COMPONENT dsram GENERIC
    component dsram generic
    (
    (
        WIDTH : positive;
        WIDTH : positive;
        SIZE  : positive
        SIZE  : positive
    );
    );
    PORT
    port
    (
    (
        dat_o   : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
        dat_o   : out std_logic_vector(WIDTH - 1 downto 0);
        adr_i   : IN std_logic_vector(SIZE - 1 DOWNTO 0);
        adr_i   : in std_logic_vector(SIZE - 1 downto 0);
        ena_i   : IN std_logic;
        ena_i   : in std_logic;
        dat_w_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
        dat_w_i : in std_logic_vector(WIDTH - 1 downto 0);
        adr_w_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
        adr_w_i : in std_logic_vector(SIZE - 1 downto 0);
        wre_i   : IN std_logic;
        wre_i   : in std_logic;
        clk_i   : IN std_logic
        clk_i   : in std_logic
    );
    );
    END COMPONENT;
    end component;
 
 
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
-- FUNCTIONS IN STD_PKG
-- FUNCTIONS IN STD_PKG
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
 
 
    FUNCTION v_or(d : std_logic_vector) RETURN std_logic;
    function v_or(d : std_logic_vector) return std_logic;
    FUNCTION is_zero(d : std_logic_vector) RETURN std_logic;
    function is_zero(d : std_logic_vector) return std_logic;
    FUNCTION is_not_zero(d : std_logic_vector) RETURN std_logic;
    function is_not_zero(d : std_logic_vector) return std_logic;
    FUNCTION my_conv_integer(a: std_logic_vector) RETURN integer;
    function my_conv_integer(a: std_logic_vector) return integer;
    FUNCTION notx(d : std_logic_vector) RETURN boolean;
    function notx(d : std_logic_vector) return boolean;
    FUNCTION compare(a, b : std_logic_vector) RETURN std_logic;
    function compare(a, b : std_logic_vector) return std_logic;
    FUNCTION multiply(a, b : std_logic_vector) RETURN std_logic_vector;
    function multiply(a, b : std_logic_vector) return std_logic_vector;
    FUNCTION sign_extend(value: std_logic_vector; fill: std_logic; size: positive) RETURN std_logic_vector;
    function sign_extend(value: std_logic_vector; fill: std_logic; size: positive) return std_logic_vector;
    FUNCTION add(a, b : std_logic_vector; ci: std_logic) RETURN std_logic_vector;
    function add(a, b : std_logic_vector; ci: std_logic) return std_logic_vector;
    FUNCTION increment(a : std_logic_vector) RETURN std_logic_vector;
    function increment(a : std_logic_vector) return std_logic_vector;
    FUNCTION shift(value : std_logic_vector(31 DOWNTO 0); shamt: std_logic_vector(4 DOWNTO 0); s: std_logic; t: std_logic) RETURN std_logic_vector;
    function shift(value : std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); s: std_logic; t: std_logic) return std_logic_vector;
    FUNCTION shift_left(value : std_logic_vector(31 DOWNTO 0); shamt : std_logic_vector(4 DOWNTO 0)) RETURN std_logic_vector;
    function shift_left(value : std_logic_vector(31 downto 0); shamt : std_logic_vector(4 downto 0)) return std_logic_vector;
    FUNCTION shift_right(value : std_logic_vector(31 DOWNTO 0); shamt : std_logic_vector(4 DOWNTO 0); padding: std_logic) RETURN std_logic_vector;
    function shift_right(value : std_logic_vector(31 downto 0); shamt : std_logic_vector(4 downto 0); padding: std_logic) return std_logic_vector;
 
 
END std_Pkg;
end std_Pkg;
 
 
PACKAGE BODY std_Pkg IS
PACKAGE BODY std_Pkg IS
 
 
-- Unary OR reduction
-- Unary OR reduction
    FUNCTION v_or(d : std_logic_vector) RETURN std_logic IS
    function v_or(d : std_logic_vector) return std_logic is
        VARIABLE z : std_logic;
        variable z : std_logic;
    BEGIN
    begin
        z := '0';
        z := '0';
        IF notx (d) THEN
        if notx (d) then
            FOR i IN d'range LOOP
            for i in d'range loop
                z := z OR d(i);
                z := z or d(i);
            END LOOP;
            end loop;
        END IF;
        end if;
        RETURN z;
        return z;
    END;
    end;
 
 
-- Check for ones in the vector
-- Check for ones in the vector
    FUNCTION is_not_zero(d : std_logic_vector) RETURN std_logic IS
    function is_not_zero(d : std_logic_vector) return std_logic is
        VARIABLE z : std_logic_vector(d'range);
        variable z : std_logic_vector(d'range);
    BEGIN
    begin
        z := (OTHERS => '0');
        z := (others => '0');
        IF notx(d) THEN
        if notx(d) then
 
 
            IF d = z THEN
            if d = z then
                RETURN '0';
                return '0';
            ELSE
            else
                RETURN '1';
                return '1';
            END IF;
            end if;
 
 
        ELSE
        else
            RETURN '0';
            return '0';
        END IF;
        end if;
    END;
    end;
 
 
-- Check for ones in the vector
-- Check for ones in the vector
    FUNCTION is_zero(d : std_logic_vector) RETURN std_logic IS
    function is_zero(d : std_logic_vector) return std_logic is
    BEGIN
    begin
        RETURN NOT is_not_zero(d);
        return not is_not_zero(d);
    END;
    end;
 
 
    -- rewrite conv_integer to avoid modelsim warnings
    -- rewrite conv_integer to avoid modelsim warnings
    FUNCTION my_conv_integer(a : std_logic_vector) RETURN integer IS
    function my_conv_integer(a : std_logic_vector) return integer is
        VARIABLE res : integer RANGE 0 TO 2**a'length-1;
        variable res : integer range 0 to 2**a'length-1;
    BEGIN
    begin
        res := 0;
        res := 0;
        IF (notx(a)) THEN
        if (notx(a)) then
            res := to_integer(unsigned(a));
            res := to_integer(unsigned(a));
        END IF;
        end if;
        RETURN res;
        return res;
    END;
    end;
 
 
    FUNCTION compare(a, b : std_logic_vector) RETURN std_logic IS
    function compare(a, b : std_logic_vector) return std_logic is
        VARIABLE z : std_logic;
        variable z : std_logic;
    BEGIN
    begin
 
        if notx(a & b) and a = b then
        IF notx(a & b) AND a = b THEN
            return '1';
            RETURN '1';
        else
        ELSE
            return '0';
            RETURN '0';
        end if;
        END IF;
    end;
 
 
    END;
 
 
 
-- Unary NOT X test
-- Unary NOT X test
    FUNCTION notx(d : std_logic_vector) RETURN boolean IS
    function notx(d : std_logic_vector) return boolean is
        VARIABLE res : boolean;
        variable res : boolean;
    BEGIN
    begin
        res := true;
        res := true;
-- pragma translate_off
-- pragma translate_off
        res := NOT is_x(d);
        res := not is_x(d);
-- pragma translate_on
-- pragma translate_on
        RETURN (res);
        return (res);
    END;
    end;
 
 
-- -- 32 bit shifter
-- -- 32 bit shifter
-- -- SYNOPSIS:
-- -- SYNOPSIS:
-- --    value: value to be shifted
-- --    value: value to be shifted
-- --    shamt: shift amount
-- --    shamt: shift amount
-- --    s 0 / 1: shift right / left
-- --    s 0 / 1: shift right / left
-- --    t 0 / 1: shift logical / arithmetic
-- --    t 0 / 1: shift logical / arithmetic
-- -- PSEUDOCODE (from microblaze reference guide)
-- -- PSEUDOCODE (from microblaze reference guide)
-- --     if S = 1 then
-- --     if S = 1 then
-- --          (rD) ← (rA) << (rB)[27:31]
-- --          (rD) = (rA) << (rB)[27:31]
-- --     else
-- --     else
-- --      if T = 1 then
-- --      if T = 1 then
-- --         if ((rB)[27:31]) ≠ 0 then
-- --         if ((rB)[27:31]) != 0 then
-- --              (rD)[0:(rB)[27:31]-1] ← (rA)[0]
-- --              (rD)[0:(rB)[27:31]-1] = (rA)[0]
-- --              (rD)[(rB)[27:31]:31] ← (rA) >> (rB)[27:31]
-- --              (rD)[(rB)[27:31]:31] = (rA) >> (rB)[27:31]
-- --         else
-- --         else
-- --              (rD) ← (rA)
-- --              (rD) = (rA)
-- --      else
-- --      else
-- --         (rD) ← (rA) >> (rB)[27:31]
-- --         (rD) = (rA) >> (rB)[27:31]
 
 
    FUNCTION shift(value: std_logic_vector(31 DOWNTO 0); shamt: std_logic_vector(4 DOWNTO 0); s: std_logic; t: std_logic) RETURN std_logic_vector IS
    function shift(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); s: std_logic; t: std_logic) return std_logic_vector is
    BEGIN
    begin
        IF s = '1' THEN
        if s = '1' then
            -- left arithmetic or logical shift
            -- left arithmetic or logical shift
            RETURN shift_left(value, shamt);
            return shift_left(value, shamt);
        ELSE
        else
            IF t = '1' THEN
            if t = '1' then
                -- right arithmetic shift
                -- right arithmetic shift
                RETURN shift_right(value, shamt, value(31));
                return shift_right(value, shamt, value(31));
            ELSE
            else
                -- right logical shift
                -- right logical shift
                RETURN shift_right(value, shamt, '0');
                return shift_right(value, shamt, '0');
            END IF;
            end if;
        END IF;
        end if;
    END;
    end;
 
 
    FUNCTION shift_left(value: std_logic_vector(31 DOWNTO 0); shamt: std_logic_vector(4 DOWNTO 0)) RETURN std_logic_vector IS
    function shift_left(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0)) return std_logic_vector is
        VARIABLE result: std_logic_vector(31 DOWNTO 0);
        variable result: std_logic_vector(31 downto 0);
        VARIABLE paddings: std_logic_vector(15 DOWNTO 0);
        variable paddings: std_logic_vector(15 downto 0);
    BEGIN
    begin
 
        paddings := (others => '0');
        paddings := (OTHERS => '0');
 
        result := value;
        result := value;
        IF (shamt(4) = '1') THEN result := result(15 DOWNTO 0) & paddings(15 DOWNTO 0); END IF;
        if (shamt(4) = '1') then result := result(15 downto 0) & paddings(15 downto 0); end if;
        IF (shamt(3) = '1') THEN result := result(23 DOWNTO 0) & paddings( 7 DOWNTO 0); END IF;
        if (shamt(3) = '1') then result := result(23 downto 0) & paddings( 7 downto 0); end if;
        IF (shamt(2) = '1') THEN result := result(27 DOWNTO 0) & paddings( 3 DOWNTO 0); END IF;
        if (shamt(2) = '1') then result := result(27 downto 0) & paddings( 3 downto 0); end if;
        IF (shamt(1) = '1') THEN result := result(29 DOWNTO 0) & paddings( 1 DOWNTO 0); END IF;
        if (shamt(1) = '1') then result := result(29 downto 0) & paddings( 1 downto 0); end if;
        IF (shamt(0) = '1') THEN result := result(30 DOWNTO 0) & paddings( 0 );         END IF;
        if (shamt(0) = '1') then result := result(30 downto 0) & paddings( 0 );         end if;
        RETURN result;
        return result;
 
    end;
    END;
 
 
    function shift_right(value: std_logic_vector(31 downto 0); shamt: std_logic_vector(4 downto 0); padding: std_logic) return std_logic_vector is
    FUNCTION shift_right(value: std_logic_vector(31 DOWNTO 0); shamt: std_logic_vector(4 DOWNTO 0); padding: std_logic) RETURN std_logic_vector IS
        variable result: std_logic_vector(31 downto 0);
        VARIABLE result: std_logic_vector(31 DOWNTO 0);
        variable paddings: std_logic_vector(15 downto 0);
        VARIABLE paddings: std_logic_vector(15 DOWNTO 0);
    begin
    BEGIN
        paddings := (others => padding);
 
 
        paddings := (OTHERS => padding);
 
        result := value;
        result := value;
        IF (shamt(4) = '1') THEN result := paddings(15 DOWNTO 0) & result(31 DOWNTO 16); END IF;
        if (shamt(4) = '1') then result := paddings(15 downto 0) & result(31 downto 16); end if;
        IF (shamt(3) = '1') THEN result := paddings( 7 DOWNTO 0) & result(31 DOWNTO  8); END IF;
        if (shamt(3) = '1') then result := paddings( 7 downto 0) & result(31 downto  8); end if;
        IF (shamt(2) = '1') THEN result := paddings( 3 DOWNTO 0) & result(31 DOWNTO  4); END IF;
        if (shamt(2) = '1') then result := paddings( 3 downto 0) & result(31 downto  4); end if;
        IF (shamt(1) = '1') THEN result := paddings( 1 DOWNTO 0) & result(31 DOWNTO  2); END IF;
        if (shamt(1) = '1') then result := paddings( 1 downto 0) & result(31 downto  2); end if;
        IF (shamt(0) = '1') THEN result := paddings( 0 )         & result(31 DOWNTO  1); END IF;
        if (shamt(0) = '1') then result := paddings( 0 )         & result(31 downto  1); end if;
        RETURN result;
        return result;
 
    end;
    END;
 
 
    function multiply(a, b: std_logic_vector) return std_logic_vector is
    FUNCTION multiply(a, b: std_logic_vector) RETURN std_logic_vector IS
        variable x: std_logic_vector (a'length + b'length - 1 downto 0);
        VARIABLE x: std_logic_vector (a'length + b'length - 1 DOWNTO 0);
    begin
    BEGIN
 
        x := std_logic_vector(signed(a) * signed(b));
        x := std_logic_vector(signed(a) * signed(b));
        RETURN x(31 DOWNTO 0);
        return x(31 downto 0);
    END;
    end;
 
 
    FUNCTION sign_extend(value: std_logic_vector; fill: std_logic; size: positive) RETURN std_logic_vector IS
    function sign_extend(value: std_logic_vector; fill: std_logic; size: positive) return std_logic_vector is
        VARIABLE a: std_logic_vector (size - 1 DOWNTO 0);
        variable a: std_logic_vector (size - 1 downto 0);
    BEGIN
    begin
        a(size - 1 DOWNTO value'length) := (OTHERS => fill);
        a(size - 1 downto value'length) := (others => fill);
        a(value'length - 1 DOWNTO 0) := value;
        a(value'length - 1 downto 0) := value;
        return a;
        return a;
    END;
    end;
 
 
    FUNCTION add(a, b : std_logic_vector; ci: std_logic) RETURN std_logic_vector IS
    function add(a, b : std_logic_vector; ci: std_logic) return std_logic_vector is
        VARIABLE x : std_logic_vector(a'length + 1 DOWNTO 0);
        variable x : std_logic_vector(a'length + 1 downto 0);
    BEGIN
    begin
        x := (OTHERS => '0');
        x := (others => '0');
        IF notx (a & b & ci) THEN
        if notx (a & b & ci) then
            x := std_logic_vector(signed('0' & a & '1') + signed('0' & b & ci));
            x := std_logic_vector(signed('0' & a & '1') + signed('0' & b & ci));
        END IF;
        end if;
        RETURN x(a'length + 1 DOWNTO 1);
        return x(a'length + 1 downto 1);
    END;
    end;
 
 
    FUNCTION increment(a : std_logic_vector) RETURN std_logic_vector IS
    function increment(a : std_logic_vector) return std_logic_vector is
        VARIABLE x : std_logic_vector(a'length-1 DOWNTO 0);
        variable x : std_logic_vector(a'length-1 downto 0);
    BEGIN
    begin
        x := (OTHERS => '0');
        x := (others => '0');
        IF notx (a) THEN
        if notx (a) then
            x := std_logic_vector(signed(a) + 1);
            x := std_logic_vector(signed(a) + 1);
        END IF;
        end if;
        RETURN x;
        return x;
    END;
    end;
 
 
END std_Pkg;
 
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end std_Pkg;
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