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[/] [mcs-4/] [trunk/] [rtl/] [verilog/] [i4004/] [instruction_decode.v] - Diff between revs 5 and 6
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Rev 6 |
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// 4004 Instruction Decoder
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// 4004 Instruction Decoder
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//
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//
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// This file is part of the MCS-4 project hosted at OpenCores:
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// This file is part of the MCS-4 project hosted at OpenCores:
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// http://www.opencores.org/cores/mcs-4/
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// http://www.opencores.org/cores/mcs-4/
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//
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//
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// Copyright © 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
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// Copyright © 2012, 2021 by Reece Pollack <rrpollack@opencores.org>
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//
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//
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// These materials are provided under the Creative Commons
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// These materials are provided under the Creative Commons
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// "Attribution-NonCommercial-ShareAlike" Public License. They
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// "Attribution-NonCommercial-ShareAlike" (CC BY-NC-SA) Public License.
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// are NOT "public domain" and are protected by copyright.
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// They are NOT "public domain", and are protected by copyright.
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//
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//
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// This work based on materials provided by Intel Corporation and
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// This work based on materials provided by Intel Corporation and
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// others under the same license. See the file doc/License for
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// others under the same license. See the file doc/License for
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// details of this license.
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// details of this license.
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//
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//
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reg n0405;
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reg n0405;
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always @(posedge sysclk) begin
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always @(posedge sysclk) begin
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if (clk2)
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if (clk2)
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n0405 <= n0413;
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n0405 <= n0413;
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end
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end
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always @(posedge sysclk) begin
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always @(*) begin
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if (clk1)
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if (clk1)
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n0397 <= ~n0405;
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n0397 <= ~n0405;
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end
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end
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assign cn_n = ~n0397;
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assign cn_n = ~n0397;
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