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// 4004 Instruction Pointer Array
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// 4004 Instruction Pointer Array
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//
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//
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// This file is part of the MCS-4 project hosted at OpenCores:
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// This file is part of the MCS-4 project hosted at OpenCores:
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// http://www.opencores.org/cores/mcs-4/
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// http://www.opencores.org/cores/mcs-4/
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//
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//
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// Copyright © 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
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// Copyright © 2012, 2021 by Reece Pollack <rrpollack@opencores.org>
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//
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//
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// These materials are provided under the Creative Commons
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// These materials are provided under the Creative Commons
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// "Attribution-NonCommercial-ShareAlike" Public License. They
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// "Attribution-NonCommercial-ShareAlike" (CC BY-NC-SA) Public License.
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// are NOT "public domain" and are protected by copyright.
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// They are NOT "public domain", and are protected by copyright.
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//
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//
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// This work based on materials provided by Intel Corporation and
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// This work based on materials provided by Intel Corporation and
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// others under the same license. See the file doc/License for
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// others under the same license. See the file doc/License for
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// details of this license.
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// details of this license.
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//
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//
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| Line 57... |
Line 57... |
wire inh = (jin_fin & sc) | ((jun_jms | (jcn_isz & ~cn_n)) & dc);
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wire inh = (jin_fin & sc) | ((jun_jms | (jcn_isz & ~cn_n)) & dc);
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// Row Counter stuff
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// Row Counter stuff
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wire [1:0] addr_ptr; // Effective Address counter
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wire [1:0] addr_ptr; // Effective Address counter
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wire addr_ptr_step; // CLK2(JMS&DC&M22+BBL(M22+X12+X22))
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wire addr_ptr_step; // CLK2(JMS&DC&M22+BBL(M22+X12+X22))
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wire n0459;
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wire n0466;
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assign addr_ptr_step = ~(~clk2 | ~(((m22 | x12 | x22) & bbl) |
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assign addr_ptr_step = ~(~clk2 | ~(((m22 | x12 | x22) & bbl) |
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(m22 & dc & jms)));
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(m22 & dc & jms)));
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counter addr_ptr_0 (
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counter addr_ptr_0 (
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.sysclk(sysclk),
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.sysclk(sysclk),
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.step_a(clk1),
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.step_a_in(clk1),
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.step_b(addr_ptr_step),
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.step_b_in(addr_ptr_step),
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.q(addr_ptr[0])
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.step_a_out(n0459),
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.step_b_out(n0466),
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.q(),
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.qn(addr_ptr[0])
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);
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);
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counter addr_ptr_1 (
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counter addr_ptr_1 (
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.sysclk(sysclk),
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.sysclk(sysclk),
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.step_a( addr_ptr[0]),
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.step_a_in(n0459),
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.step_b(~addr_ptr[0]),
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.step_b_in(n0466),
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.q(addr_ptr[1])
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.step_a_out(),
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.step_b_out(),
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.q(),
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.qn(addr_ptr[1])
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);
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);
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// Refresh counter stuff
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// Refresh counter stuff
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wire [1:0] addr_rfsh; // Row Refresh counter
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wire [1:0] addr_rfsh; // Row Refresh counter
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wire addr_rfsh_step; // (~INH)&X32&CLK2
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wire addr_rfsh_step; // (~INH)&X32&CLK2
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wire n0455;
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wire n0463;
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assign addr_rfsh_step = ~inh & x32 & clk2;
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assign addr_rfsh_step = ~inh & x32 & clk2;
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counter addr_rfsh_0 (
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counter addr_rfsh_0 (
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.sysclk(sysclk),
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.sysclk(sysclk),
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.step_a(clk1),
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.step_a_in(clk1),
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.step_b(addr_rfsh_step),
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.step_b_in(addr_rfsh_step),
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.q(addr_rfsh[0])
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.step_a_out(n0455),
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.step_b_out(n0463),
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.q(),
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.qn(addr_rfsh[0])
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);
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);
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counter addr_rfsh_1 (
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counter addr_rfsh_1 (
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.sysclk(sysclk),
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.sysclk(sysclk),
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.step_a( addr_rfsh[0]),
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.step_a_in(n0455),
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.step_b(~addr_rfsh[0]),
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.step_b_in(n0463),
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.q(addr_rfsh[1])
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.step_a_out(),
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.step_b_out(),
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.q(),
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.qn(addr_rfsh[1])
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);
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);
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// Row selection mux
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// Row selection mux
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reg [1:0] row; // {N0409, N0420}
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reg [1:0] row; // {N0409, N0420}
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always @(posedge sysclk) begin
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always @(posedge sysclk) begin
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| Line 157... |
Line 173... |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m12)));
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(((jcn_isz & n0322) | (jun_jms & ~sc)) & m12)));
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wire wadb2 = ~(~clk2 | ~(a32 | (jun_jms & ~sc & x22)));
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wire wadb2 = ~(~clk2 | ~(a32 | (jun_jms & ~sc & x22)));
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// Manage the row data buffer
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// Manage the row data buffer
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wire [11:0] row_data = dram_array[row];
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always @(posedge sysclk) begin
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always @(posedge sysclk) begin
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if (precharge)
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if (precharge)
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dram_temp <= 12'b0;
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dram_temp <= 12'b0;
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if (row_read)
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if (row_read)
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dram_temp <= dram_array[row];
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dram_temp <= row_data;
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if (wadb0)
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if (wadb0)
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dram_temp[ 3:0] <= ~din_n;
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dram_temp[ 3:0] <= ~din_n;
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if (wadb1)
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if (wadb1)
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dram_temp[ 7:4] <= ~din_n;
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dram_temp[ 7:4] <= ~din_n;
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Line 197... |
dram_array[row] <= dram_temp;
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dram_array[row] <= dram_temp;
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end
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end
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// Manage the data output mux
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// Manage the data output mux
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reg [3:0] dout;
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reg [3:0] dout;
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always @* begin
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always @(*) begin
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(* PARALLEL_CASE *)
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(* PARALLEL_CASE *)
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case (1'b1)
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case (1'b1)
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radb0: dout = dram_temp[ 3:0];
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radb0: dout = dram_temp[ 3:0];
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radb1: dout = dram_temp[ 7:4];
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radb1: dout = dram_temp[ 7:4];
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radb2: dout = dram_temp[11:8];
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radb2: dout = dram_temp[11:8];
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