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`timescale 1ns / 1ps
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`default_nettype none
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////////////////////////////////////////////////////////////////////////
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//
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// 4004 Scratchpad Register Array
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//
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// This file is part of the MCS-4 project hosted at OpenCores:
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// http://www.opencores.org/cores/mcs-4/
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//
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// Copyright © 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
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//
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// These materials are provided under the Creative Commons
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// "Attribution-NonCommercial-ShareAlike" Public License. They
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// are NOT "public domain" and are protected by copyright.
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//
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// This work based on materials provided by Intel Corporation and
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// others under the same license. See the file doc/License for
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// details of this license.
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//
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////////////////////////////////////////////////////////////////////////
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module scratchpad (
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input wire sysclk, // 50 MHz FPGA clock
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// Inputs from the Timing and I/O board
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input wire clk1,
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input wire clk2,
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input wire a12,
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input wire a22,
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input wire a32,
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input wire m12,
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input wire m22,
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input wire x12,
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input wire x22,
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input wire x32,
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input wire poc, // Power-On Clear (reset)
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input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
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// Common 4-bit data bus
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inout wire [3:0] data,
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// Inputs from the Instruction Decode board
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input wire n0636, // JIN+FIN
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input wire sc_m22_clk2, // SC&M22&CLK2
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input wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
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input wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
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input wire inc_isz_xch, // INC+ISZ+XCH
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input wire opa0_n, // ~OPA.0
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input wire sc, // SC (Single Cycle)
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input wire dc // DC (Double Cycle, ~SC)
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);
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reg [7:0] dram_array [0:7];
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reg [7:0] dram_temp;
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reg [3:0] din_n;
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// Refresh counter stuff
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wire [2:0] reg_rfsh; // Row Refresh counter
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wire reg_rfsh_step; // SC&A12&CLK2
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assign reg_rfsh_step = sc & a12 & clk2;
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counter reg_rfsh_0 (
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.sysclk(sysclk),
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.step_a(clk1),
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.step_b(reg_rfsh_step),
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.q(reg_rfsh[0])
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);
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counter reg_rfsh_1 (
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.sysclk(sysclk),
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.step_a( reg_rfsh[0]),
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.step_b(~reg_rfsh[0]),
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.q(reg_rfsh[1])
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);
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counter reg_rfsh_2 (
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.sysclk(sysclk),
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.step_a( reg_rfsh[1]),
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.step_b(~reg_rfsh[1]),
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.q(reg_rfsh[2])
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);
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// Row selection mux
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reg [2:0] row; // {N0646, N0617, N0582}
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always @(posedge sysclk) begin
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if (sc & a22)
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row <= reg_rfsh;
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if (sc_m22_clk2)
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row <= data[3:1];
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end
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// Row Precharge/Read/Write stuff
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wire precharge; // SC(A22+M22)CLK2
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wire row_read; // (~POC)&CLK2&SC(A32+X12)
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wire row_write; // CLK2&SC(A12+M12)
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assign precharge = sc & (a22 | m22) & clk2;
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assign row_read = ~(poc | ~(clk2 & sc & (a32 | x12)));
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assign row_write = sc & (a12 | m12) & clk2;
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// Column Read selection stuff
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reg n0615;
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always @(posedge sysclk) begin
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if (clk2)
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n0615 <= ~(x12 & (fin_fim_src_jin |
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(opa0_n & inc_isz_add_sub_xch_ld)));
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end
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wire rrab0 = ~(dc | n0615 | clk2);
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reg n0592;
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always @(posedge sysclk) begin
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if (clk2)
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n0592 <= ~((x22 & fin_fim_src_jin) |
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(~opa0_n & x12 & inc_isz_add_sub_xch_ld));
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end
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wire rrab1 = ~(dc | n0592 | clk2);
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// Column Write selection stuff
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wire n0564 = opa0_n & fin_fim_src_jin & dc;
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wire n0568 = inc_isz_xch & x32 & sc;
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wire wrab0 = clk2 & ((m12 & n0564) | ( opa0_n & n0568));
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wire wrab1 = clk2 & ((m22 & n0564) | (~opa0_n & n0568));
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// Force row 0 if FIN&X12
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wire fin_x12 = (n0636 & opa0_n) & x12;
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// Manage the row data buffer
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always @(posedge sysclk) begin
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if (precharge)
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dram_temp <= 8'b0;
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if (row_read)
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dram_temp <= dram_array[fin_x12 ? 3'b000 : row];
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if (wrab0)
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dram_temp[ 7:4] <= ~din_n;
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if (wrab1)
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dram_temp[ 3:0] <= ~din_n;
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end
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// Handle row writes
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always @(posedge sysclk) begin
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if (row_write)
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dram_array[row] <= dram_temp;
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end
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// Manage the data output mux
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reg [3:0] dout;
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always @* begin
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(* PARALLEL_CASE *)
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case (1'b1)
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rrab0: dout = dram_temp[ 7:4];
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rrab1: dout = dram_temp[ 3:0];
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default: dout = 4'bzzzz;
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endcase
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end
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assign data = dout;
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// Data In latch
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always @(posedge sysclk) begin
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if (m12_m22_clk1_m11_m12)
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din_n <= ~data;
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end
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endmodule
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No newline at end of file
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No newline at end of file
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