Line 5... |
Line 5... |
// 4004 Scratchpad Register Array
|
// 4004 Scratchpad Register Array
|
//
|
//
|
// This file is part of the MCS-4 project hosted at OpenCores:
|
// This file is part of the MCS-4 project hosted at OpenCores:
|
// http://www.opencores.org/cores/mcs-4/
|
// http://www.opencores.org/cores/mcs-4/
|
//
|
//
|
// Copyright © 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
|
// Copyright © 2012, 2021 by Reece Pollack <rrpollack@opencores.org>
|
//
|
//
|
// These materials are provided under the Creative Commons
|
// These materials are provided under the Creative Commons
|
// "Attribution-NonCommercial-ShareAlike" Public License. They
|
// "Attribution-NonCommercial-ShareAlike" (CC BY-NC-SA) Public License.
|
// are NOT "public domain" and are protected by copyright.
|
// They are NOT "public domain", and are protected by copyright.
|
//
|
//
|
// This work based on materials provided by Intel Corporation and
|
// This work based on materials provided by Intel Corporation and
|
// others under the same license. See the file doc/License for
|
// others under the same license. See the file doc/License for
|
// details of this license.
|
// details of this license.
|
//
|
//
|
Line 55... |
Line 55... |
reg [3:0] din_n;
|
reg [3:0] din_n;
|
|
|
// Refresh counter stuff
|
// Refresh counter stuff
|
wire [2:0] reg_rfsh; // Row Refresh counter
|
wire [2:0] reg_rfsh; // Row Refresh counter
|
wire reg_rfsh_step; // SC&A12&CLK2
|
wire reg_rfsh_step; // SC&A12&CLK2
|
|
wire n0571;
|
|
wire n0574;
|
|
wire n0600;
|
|
wire n0610;
|
|
|
assign reg_rfsh_step = sc & a12 & clk2;
|
assign reg_rfsh_step = sc & a12 & clk2;
|
|
|
counter reg_rfsh_0 (
|
counter reg_rfsh_0 (
|
.sysclk(sysclk),
|
.sysclk(sysclk),
|
.step_a(clk1),
|
.step_a_in(clk1),
|
.step_b(reg_rfsh_step),
|
.step_b_in(reg_rfsh_step),
|
.q(reg_rfsh[0])
|
.step_a_out(n0571),
|
|
.step_b_out(n0574),
|
|
.q(reg_rfsh[0]),
|
|
.qn()
|
);
|
);
|
counter reg_rfsh_1 (
|
counter reg_rfsh_1 (
|
.sysclk(sysclk),
|
.sysclk(sysclk),
|
.step_a( reg_rfsh[0]),
|
.step_a_in(n0571),
|
.step_b(~reg_rfsh[0]),
|
.step_b_in(n0574),
|
.q(reg_rfsh[1])
|
.step_a_out(n0600),
|
|
.step_b_out(n0610),
|
|
.q(reg_rfsh[1]),
|
|
.qn()
|
);
|
);
|
counter reg_rfsh_2 (
|
counter reg_rfsh_2 (
|
.sysclk(sysclk),
|
.sysclk(sysclk),
|
.step_a( reg_rfsh[1]),
|
.step_a_in(n0600),
|
.step_b(~reg_rfsh[1]),
|
.step_b_in(n0610),
|
.q(reg_rfsh[2])
|
.step_a_out(),
|
|
.step_b_out(),
|
|
.q(reg_rfsh[2]),
|
|
.qn()
|
);
|
);
|
|
|
// Row selection mux
|
// Row selection mux
|
reg [2:0] row; // {N0646, N0617, N0582}
|
reg [2:0] row; // {N0646, N0617, N0582}
|
always @(posedge sysclk) begin
|
always @(posedge sysclk) begin
|
Line 126... |
Line 139... |
|
|
// Force row 0 if FIN&X12
|
// Force row 0 if FIN&X12
|
wire fin_x12 = (n0636 & opa0_n) & x12;
|
wire fin_x12 = (n0636 & opa0_n) & x12;
|
|
|
// Manage the row data buffer
|
// Manage the row data buffer
|
|
wire [7:0] row_data = dram_array[fin_x12 ? 3'b000 : row];
|
always @(posedge sysclk) begin
|
always @(posedge sysclk) begin
|
if (precharge)
|
if (precharge)
|
dram_temp <= 8'b0;
|
dram_temp <= 8'b0;
|
|
|
if (row_read)
|
if (row_read)
|
dram_temp <= dram_array[fin_x12 ? 3'b000 : row];
|
dram_temp <= row_data;
|
|
|
if (wrab0)
|
if (wrab0)
|
dram_temp[ 7:4] <= ~din_n;
|
dram_temp[ 7:4] <= ~din_n;
|
if (wrab1)
|
if (wrab1)
|
dram_temp[ 3:0] <= ~din_n;
|
dram_temp[ 3:0] <= ~din_n;
|