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`timescale 1ns / 1ps
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`default_nettype none
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////////////////////////////////////////////////////////////////////////
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//
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// 4004 Timing and I/O Interfaces
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//
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// This file is part of the MCS-4 project hosted at OpenCores:
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// http://www.opencores.org/cores/mcs-4/
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//
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// Copyright © 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
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//
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// These materials are provided under the Creative Commons
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// "Attribution-NonCommercial-ShareAlike" Public License. They
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// are NOT "public domain" and are protected by copyright.
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//
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// This work based on materials provided by Intel Corporation and
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// others under the same license. See the file doc/License for
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// details of this license.
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//
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////////////////////////////////////////////////////////////////////////
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module timing_io(
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input wire sysclk,
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input wire clk1_pad,
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input wire clk2_pad,
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input wire poc_pad,
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input wire ior,
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// Timing and I/O Board Outputs
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output wire clk1,
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output wire clk2,
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output wire a12,
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output wire a22,
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output wire a32,
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output wire m12,
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output wire m22,
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output wire x12,
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output wire x22,
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output wire x32,
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output wire gate,
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output reg poc,
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// External I/O Pad conditioning
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inout wire [3:0] data,
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inout wire [3:0] data_pad,
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input wire test_pad,
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output reg n0432,
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output reg sync_pad,
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input wire cmrom,
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output wire cmrom_pad,
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input wire cmram0,
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output wire cmram0_pad,
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input wire cmram1,
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output wire cmram1_pad,
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input wire cmram2,
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output wire cmram2_pad,
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input wire cmram3,
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output wire cmram3_pad
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);
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// Simple pass-throughs
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assign clk1 = clk1_pad;
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assign clk2 = clk2_pad;
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assign cmrom_pad = cmrom;
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assign cmram0_pad = cmram0;
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assign cmram1_pad = cmram1;
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assign cmram2_pad = cmram2;
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assign cmram3_pad = cmram3;
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// Generate the 8 execution phase indicators
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reg [0:7] master = 8'h00;
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reg [0:7] slave = 8'h00;
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always @(posedge sysclk) begin
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if (clk2)
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master <= {~|slave[0:6], slave[0:6]};
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else
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sync_pad <= master[7];
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if (clk1)
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slave <= master;
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end
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assign a12 = slave[0];
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assign a22 = slave[1];
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assign a32 = slave[2];
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assign m12 = slave[3];
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assign m22 = slave[4];
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assign x12 = slave[5];
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assign x22 = slave[6];
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assign x32 = slave[7];
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// Generate the DRAM Input Gate signal
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// Properly called M12+M22+CLK1~(M11&M12)
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wire n0279 = ~(a32 | m12);
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reg n0278;
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always @(posedge sysclk) begin
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if (clk2)
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n0278 <= n0279;
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end
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wire n0708 = ~((n0278 & clk1) | m12 | m22);
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assign gate = ~n0708;
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// Generate a clean POC signal
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always @(posedge sysclk) begin
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if (poc_pad) poc <= 1'b1;
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else if (a12) poc <= 1'b0;
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else poc <= poc;
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end
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// Generate a clean ~TEST signal (n0432)
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always @(posedge sysclk) begin
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n0432 <= ~test_pad;
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end
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// Manage the Data I/O pads
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reg L;
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always @(posedge sysclk) begin
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if (clk2)
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L <= a32 | m12 | (x12 & (ior | poc));
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end
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wire n0702 = ~clk2;
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reg n0685;
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reg n0699;
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reg n0707;
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always @(posedge sysclk) begin
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if (clk1) begin
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n0685 <= ~L;
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n0707 <= L;
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end
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if (n0702)
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n0699 <= ~L;
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end
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wire n0700 = n0707 | (L & n0702) | poc;
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wire n0659 = (clk2 & n0685) | (clk1 & L);
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wire n0676 = clk1 | n0685 | n0699;
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// Incoming data from the external pads
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reg [3:0] data_in;
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always @* begin
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if (n0659) data_in = 4'b1111;
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else if (n0676) data_in = 4'bzzzz;
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else if (poc) data_in = 4'b0000;
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else data_in = data_pad;
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end
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assign data = data_in;
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// Outgoing data to the external pads
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reg [3:0] data_out;
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always @(posedge sysclk) begin
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if (n0702)
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data_out <= data;
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end
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assign data_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
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endmodule
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