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##############################################################################################
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# In order to create a new project, change the first three macros in this file, the content #
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# of the UCF file and the name and content of the VHD files in src #
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# Don't forget to execute "source bin/load_modules" manual from the shell #
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##############################################################################################
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TOP=processor_E#change to the name of the TOP-Entity
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DEVICE=3s50tq144-4
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#DEVICE=xc3s4000-fg676-4#change to the device id found on the chip
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#VHDLSYNFILES=src/cpu_types.vhd src/components.vhd src/processor_E.vhd src/processor.model.vhd src/ram.vhd src/rom.vhd #reference model for simulation
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#VHDLSYNFILES=src/cpu_types.vhd src/components.vhd src/processor_E.vhd src/processor_E_backan.vhd src/ram.vhd src/rom.vhd#backannotated simulation after synthesis with Precision
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#VHDLSYNFILES=src/cpu_types.vhd src/components.vhd src/processor_E.vhd src/processor_E_backannotated.vhd src/ram.vhd src/rom.vhd#backannotated simulation after synthesis with XST
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VHDLSYNFILES=src/cpu_types.vhd src/alu.vhd src/control.vhd src/pc.vhd src/ram_control.vhd src/reg.vhd src/components.vhd src/processor_E.vhd src/ram.vhd src/rom.vhd #synthesis and pre-synthesis simulation
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OPTMODE=Speed
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OPTLEVEL=1
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EFFORT=high
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UCF=src/$(TOP).ucf
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SCRIPTFILE=$(TOP).scr
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PROJECTFILE=$(TOP).prj
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LOGFILE=$(TOP).log
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TOPSIM=$(TOP)_tb
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DOFILE=src/$(TOP).do
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BITGEN=src/$(TOP).ut
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ALLFILES=$(VHDLSYNFILES) src/$(TOPSIM).vhd
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SHELL=/bin/bash
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all: help
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help:
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@echo
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@echo " make help : prints this help menu "
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@echo " make use-vsim : simulate with Modelsim in batch mode, use >>do it<< to reload"
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@echo " make use-vsim-gui : simulate with Modelsim and GUI"
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@echo " make use-xst : synthesize with xst "
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@echo " make implement : final step"
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@echo " make ml : prints loaded modules. Use source bin/load_modules if modules are not loaded "
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@echo " make files : prints info about the used files "
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@echo " make vsim-help : prints appropriate steps for simulation"
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@echo " make warnings-xst : prints warnings and info from the XST log file"
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@echo " make warnings-implement : prints warnings and info from the PAR log file"
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@echo " make clear : clears all XST output files"
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@echo
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use-xst: $(VHDLSYNFILES)
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@rm -f $(SCRIPTFILE)
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@rm -f $(LOGFILE)
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@rm -f $(PROJECTFILE)
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@for i in $(VHDLSYNFILES); do bin/xstvhdl $$i >> $(PROJECTFILE); done
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@echo run -ifn $(PROJECTFILE) -ifmt vhdl -ofn $(TOP).ngc -ofmt NGC -p $(DEVICE) -opt_mode $(OPTMODE) -opt_level $(OPTLEVEL) -top $(TOP) -rtlview yes > $(SCRIPTFILE)
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@xst -ifn $(SCRIPTFILE) -ofn $(LOGFILE)
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implement: $(TOP).ngc
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@mv -f src/*.ucf $(UCF)TMP
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@mv -f $(UCF)TMP $(UCF)
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@mv -f src/*.ut $(BITGEN)TMP
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@mv -f $(BITGEN)TMP $(BITGEN)
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bin/route_ngc $(TOP) $(UCF) $(DEVICE) $(EFFORT) $(BITGEN)
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ml:
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@/home/4all/packages/modules-2.0/sun5/bin/modulecmd tcsh list
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use-vsim: it $(ALLFILES)
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@rm -f it
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@for i in $(ALLFILES); do bin/vscript $$i >> it0; done
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@echo restart > it1
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@echo run -all > it2
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@cat it0 it1 it2 > it
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@rm -f it0 it1 it2
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@vmap -del work
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@rm -rf modelsim/
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@mkdir modelsim
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@vlib modelsim/work
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@vmap work modelsim/work
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@vcom -93 -check_synthesis -work work $(VHDLSYNFILES)
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@vcom -93 -work work src/$(TOPSIM).vhd
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@mv -f src/*.do $(DOFILE)TMP
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@mv -f $(DOFILE)TMP $(DOFILE)
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vsim -c work.$(TOPSIM) -do $(DOFILE)
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use-vsim-gui: $(ALLFILES)
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@rm -f it
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@for i in $(ALLFILES); do bin/vscript $$i >> it0; done
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@echo restart > it1
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@echo run 1000 ns > it2
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@cat it0 it1 it2 > it
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@rm -f it0 it1 it2
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@vmap -del work
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@rm -rf modelsim/
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@mkdir modelsim
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@vlib modelsim/work
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@vmap work modelsim/work
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@vcom -93 -check_synthesis -work work $(VHDLSYNFILES)
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@vcom -93 -work work src/$(TOPSIM).vhd
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@mv -f src/*.do $(DOFILE)TMP
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@mv -f $(DOFILE)TMP $(DOFILE)
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vsim -gui work.$(TOPSIM) -do it &
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# vsim -sdftyp /processor_e_tb/u_cpu=src/processor_E_backan.sdf -gui work.$(TOPSIM) -do it &
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use-vsim-cov: $(ALLFILES)
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vmap -del work
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rm -rf modelsim
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mkdir modelsim
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vlib modelsim/work
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vmap work modelsim/work
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vcom -cover bcst -f coverage.file
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vsim -coverage -gui work.$(TOPSIM)
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# load the rtl_a architecture in the tb file
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clear:
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@rm -f $(TOP).ngr $(TOP).msd $(TOP).msk $(TOP).rbt $(TOP).twr $(TOP).xpi $(TOP)_pad.csv $(TOP)_pad.txt $(TOP).bld
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@rm -f $(TOP).ngc $(TOP).ncd $(TOP).ngd $(TOP).rba $(TOP).rbd $(TOP).rbb netlist.lst $(TOP).mrp $(TOP).ll $(TOP).bit
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@rm -f $(TOP).lso $(TOP).ngm $(TOP).ngr $(TOP).pad $(TOP).par $(TOP).pcf transcript vsim.wlf $(TOP).log $(TOP).bgn *.twr *.xml *.map *.unroutes
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@rm -f $(SCRIPTFILE)
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@rm -f $(LOGFILE)
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@rm -f $(PROJECTFILE)
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files:
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@echo
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@echo $(TOP)".ngc : netlist output from XST"
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@echo $(TOP)".ngr : netlist output from XST for RTL and Technology viewers"
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@echo $(TOP)".scr : script file for XST, generated by Makefile"
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@echo $(TOP)".prj : contains the vhdl source files, generated by Makefile."
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@echo $(TOP)".log : log file, output from XST"
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@echo $(TOP)".ucf : user constraints file with pins description, write yourself"
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@echo $(TOP)".ut : config. script for BITGEN, write yourself"
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@echo "it : do-script for Modelsim in batchmode, write yourself"
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@echo $(TOP)".do : do-script for Modelsim in GUI-mode, write yourself"
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@echo $(TOP)".par : PAR report file, generated by make implement"
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@echo
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vsim-help:
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@echo
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@echo " mkdir modelsim : create main directoriy for simulation"
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@echo " vlib modelsim/work : create work library for simulation"
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@echo " vmap : prints all logical mapped librarys"
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@echo " vmap -del work : delete actual mapping for work library"
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@echo " vmap work modelsim/work : map logical library work to modelsim/work"
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@echo " vcom -93 -check_synthesis -work work : compile source vhdl files"
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@echo " vcom -93 -work work : compile top level testbench"
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@echo " do it : use in batch mode to recompile the testbench and the top entity and to restart the simulation"
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@echo
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warnings-xst:
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@grep -n -i warning *.log
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@grep -n -i info *.log
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warnings-implement:
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@grep -n -i warning *.par *.twr
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@grep -n -i info *.par *.twr
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