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/****************************************************************************
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Adders
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****************************************************************************/
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module adders (
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//Inputs
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Addend0A,
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Addend0B,
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Addend1A,
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Addend1B,
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Addend2A,
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Addend3A,
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Addend3B,
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StateAReg,
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StateBReg,
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StateCReg,
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StateDReg,
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A_Reg,
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B_Reg,
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C_Reg,
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D_Reg,
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//Outputs
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ResStateAReg,
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ResStateBReg,
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ResStateCReg,
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ResStateDReg,
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AddResFinal1,
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AddResFinal2,
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AddResFinal3
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);
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`include "ah_params.vh"
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input [STATE_DWIDTH - 1:0] Addend0A;
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input [STATE_DWIDTH - 1:0] Addend0B;
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input [STATE_DWIDTH - 1:0] Addend1A;
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input [STATE_DWIDTH - 1:0] Addend1B;
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input [STATE_DWIDTH - 1:0] Addend2A;
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input [STATE_DWIDTH - 1:0] Addend3A;
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input [STATE_DWIDTH - 1:0] Addend3B;
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input [STATE_DWIDTH - 1:0] StateAReg;
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input [STATE_DWIDTH - 1:0] StateBReg;
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input [STATE_DWIDTH - 1:0] StateCReg;
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input [STATE_DWIDTH - 1:0] StateDReg;
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input [STATE_DWIDTH - 1:0] A_Reg;
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input [STATE_DWIDTH - 1:0] B_Reg;
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input [STATE_DWIDTH - 1:0] C_Reg;
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input [STATE_DWIDTH - 1:0] D_Reg;
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output [STATE_DWIDTH - 1:0] ResStateAReg;
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output [STATE_DWIDTH - 1:0] ResStateBReg;
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output [STATE_DWIDTH - 1:0] ResStateCReg;
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output [STATE_DWIDTH - 1:0] ResStateDReg;
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output [STATE_DWIDTH - 1:0] AddResFinal1;
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output [STATE_DWIDTH - 1:0] AddResFinal2;
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output [STATE_DWIDTH - 1:0] AddResFinal3;
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wire [STATE_DWIDTH - 1:0] AddResFinal1;
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wire [STATE_DWIDTH - 1:0] AddResFinal2;
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wire [STATE_DWIDTH - 1:0] AddResFinal3;
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wire [STATE_DWIDTH - 1:0] AddRes0;
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wire [STATE_DWIDTH - 1:0] AddRes1;
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wire [STATE_DWIDTH - 1:0] AddRes2;
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wire [STATE_DWIDTH - 1:0] AddRes3;
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wire [STATE_DWIDTH - 1:0] AddRes4;
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wire [STATE_DWIDTH - 1:0] ResStateAReg;
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wire [STATE_DWIDTH - 1:0] ResStateBReg;
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wire [STATE_DWIDTH - 1:0] ResStateCReg;
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wire [STATE_DWIDTH - 1:0] ResStateDReg;
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assign AddResFinal1 = AddRes2;
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assign AddResFinal2 = AddRes3;
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assign AddResFinal3 = AddRes4;
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add32 u_adder_0 (
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.In0(Addend0A),
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.In1(Addend0B),
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.Out(AddRes0)
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);
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add32 u_adder_1 (
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.In0(Addend1A),
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.In1(Addend1B),
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.Out(AddRes1)
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);
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add32 u_adder_2 (
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.In0(AddRes1),
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.In1(AddRes0),
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.Out(AddRes2)
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);
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add32 u_adder_3 (
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.In0(Addend2A),
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.In1(AddRes2),
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.Out(AddRes3)
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);
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add32 u_adder_9 (
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.In0(Addend3A),
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.In1(Addend3B),
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.Out(AddRes4)
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);
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add32 u_adder_4 (
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.In0(StateAReg),
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.In1(A_Reg),
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.Out(ResStateAReg)
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);
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add32 u_adder_5 (
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.In0(StateBReg),
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.In1(B_Reg),
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.Out(ResStateBReg)
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);
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add32 u_adder_6 (
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.In0(StateCReg),
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.In1(C_Reg),
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.Out(ResStateCReg)
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);
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add32 u_adder_7 (
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.In0(StateDReg),
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.In1(D_Reg),
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.Out(ResStateDReg)
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);
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endmodule
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