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/********************************************************************************
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* Module Name : md5_ctrl
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* Description : MD5 computation control logic
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*
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********************************************************************************/
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module md5_ctrl (
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//Inputs
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clk,
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rst_n,
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DataVld,
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DataIn,
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ResStateAReg,
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ResStateBReg,
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ResStateCReg,
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ResStateDReg,
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//Outputs
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RoundNum,
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DataVldExt,
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Md5Data,
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MsgDgstVld,
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MsgDigest
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);
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`include "ah_params.vh"
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`include "md5_params.vh"
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`include "md5_func.vh"
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input clk;
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input rst_n;
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input DataVld;
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input [DATA_WIDTH - 1:0] DataIn;
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input [STATE_DWIDTH - 1:0] ResStateAReg;
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input [STATE_DWIDTH - 1:0] ResStateBReg;
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input [STATE_DWIDTH - 1:0] ResStateCReg;
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input [STATE_DWIDTH - 1:0] ResStateDReg;
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output [5:0] RoundNum;
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output DataVldExt;
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output [DATA_WIDTH - 1:0] Md5Data;
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output MsgDgstVld;
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output [DATA_WIDTH -1:0] MsgDigest;
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reg [5:0] RoundNum;
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reg DataVldTemp;
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reg MsgDgstVld_send;
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wire DataVldExt;
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wire [DATA_WIDTH - 1:0] Md5Data;
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wire [MD5_MSG_DIGEST -1:0] MsgDigest_wire;
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reg [DATA_WIDTH -1:0] MsgDigest;
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wire [STATE_DWIDTH - 1:0] ResStateAFlip;
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wire [STATE_DWIDTH - 1:0] ResStateBFlip;
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wire [STATE_DWIDTH - 1:0] ResStateCFlip;
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wire [STATE_DWIDTH - 1:0] ResStateDFlip;
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reg [2:0] sending_cnt;
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reg [2:0] sending_cnt_r;
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reg MsgDgstVld;
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wire MsgDgstVld_c;
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assign ResStateAFlip = byte_flip(ResStateAReg);
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assign ResStateBFlip = byte_flip(ResStateBReg);
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assign ResStateCFlip = byte_flip(ResStateCReg);
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assign ResStateDFlip = byte_flip(ResStateDReg);
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assign MsgDigest_wire = {ResStateAFlip, ResStateBFlip, ResStateCFlip, ResStateDFlip};
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assign DataVldExt = DataVld | DataVldTemp;
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assign Md5Data = DataIn;
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assign MsgDgstVld_c = (sending_cnt != 0);
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always @(posedge clk or negedge rst_n)
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begin
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if (!rst_n) begin
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RoundNum <= 0;
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DataVldTemp <= 0;
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end
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else begin
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if (DataVldExt) begin
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RoundNum <= (RoundNum == 63) ? 0 : RoundNum + 1;
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DataVldTemp <= (RoundNum != 63);
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end
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else begin
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RoundNum <= 0;
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DataVldTemp <= 0;
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end
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end
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end
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always @(posedge clk or negedge rst_n)
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begin
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if (!rst_n) begin
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MsgDgstVld_send <= 1'b0;
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MsgDgstVld <= 1'b0;
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end
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else begin
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MsgDgstVld_send <= (RoundNum == 63);
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MsgDgstVld <= MsgDgstVld_c;
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end
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end
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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sending_cnt_r <= 3'b0;
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end
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else begin
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sending_cnt_r <= sending_cnt;
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end
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end
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always @(MsgDgstVld_send or sending_cnt_r) begin
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if (MsgDgstVld_send & (sending_cnt_r ==0)) begin
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sending_cnt = 3'b001;
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end
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else if (sending_cnt_r !=0) begin
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sending_cnt = (sending_cnt_r == 3'b100) ? 0 : sending_cnt_r + 1;
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end
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else begin
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sending_cnt = 3'b0;
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end
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end
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always @(posedge clk) begin
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case (sending_cnt)
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3'b001 : begin
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MsgDigest <= MsgDigest_wire[31:0];
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end
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3'b010 : begin
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MsgDigest <= MsgDigest_wire[63:32];
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end
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3'b011 : begin
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MsgDigest <= MsgDigest_wire[95:64];
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end
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3'b100 : begin
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MsgDigest <= MsgDigest_wire[127:96];
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end
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default : begin
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MsgDigest <= 32'b0;
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end
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endcase
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end
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endmodule
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