| Line 120... |
Line 120... |
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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signal ramwe_s : STD_LOGIC;
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signal ramwe_s : STD_LOGIC;
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signal latch_done_reg : STD_LOGIC;
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signal latch_done_reg : STD_LOGIC;
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signal requestwr_reg : STD_LOGIC;
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signal requestwr_reg : STD_LOGIC;
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signal releasewr_reg : STD_LOGIC;
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signal releasewr_reg : STD_LOGIC;
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signal ready_prev_reg : STD_LOGIC;
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signal completed_reg : STD_LOGIC;
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signal completed_reg : STD_LOGIC;
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signal col_tmp_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
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signal col_tmp_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
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begin
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begin
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ready_sg:
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ready_sg:
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| Line 157... |
Line 156... |
ready_reg <= '0';
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ready_reg <= '0';
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latchbuf_reg <= (others => (others => '0'));
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latchbuf_reg <= (others => (others => '0'));
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istate_reg <= IDLE_I;
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istate_reg <= IDLE_I;
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latch_done_reg <= '0';
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latch_done_reg <= '0';
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requestwr_reg <= '0';
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requestwr_reg <= '0';
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ready_prev_reg <= '0';
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elsif clk = '1' and clk'event then
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elsif clk = '1' and clk'event then
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ready_prev_reg <= ready_reg;
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case istate_reg is
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case istate_reg is
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when IDLE_I =>
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when IDLE_I =>
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if idv = '1' then
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if idv = '1' then
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requestwr_reg <= '1';
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requestwr_reg <= '1';
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| Line 231... |
Line 227... |
col_reg <= (others => '0');
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col_reg <= (others => '0');
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row_reg <= (others => '0');
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row_reg <= (others => '0');
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state_reg <= IDLE;
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state_reg <= IDLE;
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cnt_reg <= (others => '0');
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cnt_reg <= (others => '0');
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databuf_reg <= (others => (others => '0'));
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databuf_reg <= (others => (others => '0'));
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romeaddro0 <= (others => '0');
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romeaddro1 <= (others => '0');
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romeaddro2 <= (others => '0');
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romeaddro3 <= (others => '0');
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romeaddro4 <= (others => '0');
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romeaddro5 <= (others => '0');
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romeaddro6 <= (others => '0');
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romeaddro7 <= (others => '0');
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romeaddro8 <= (others => '0');
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romoaddro0 <= (others => '0');
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romoaddro1 <= (others => '0');
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romoaddro2 <= (others => '0');
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romoaddro3 <= (others => '0');
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romoaddro4 <= (others => '0');
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romoaddro5 <= (others => '0');
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romoaddro6 <= (others => '0');
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romoaddro7 <= (others => '0');
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romoaddro8 <= (others => '0');
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ramwaddro <= (others => '0');
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ramwaddro <= (others => '0');
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ramdatai_s <= (others => '0');
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ramdatai_s <= (others => '0');
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ramwe_s <= '0';
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ramwe_s <= '0';
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releasewr_reg <= '0';
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releasewr_reg <= '0';
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completed_reg <= '0';
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completed_reg <= '0';
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| Line 289... |
Line 267... |
----------------------
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----------------------
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when GET_ROM =>
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when GET_ROM =>
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ramwe_s <='0';
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ramwe_s <='0';
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-- read precomputed MAC results from LUT
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romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(0)(0) &
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databuf_reg(1)(0) &
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databuf_reg(2)(0) &
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databuf_reg(3)(0);
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romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(0)(1) &
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databuf_reg(1)(1) &
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databuf_reg(2)(1) &
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databuf_reg(3)(1);
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romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(0)(2) &
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databuf_reg(1)(2) &
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databuf_reg(2)(2) &
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databuf_reg(3)(2);
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romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(0)(3) &
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databuf_reg(1)(3) &
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databuf_reg(2)(3) &
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databuf_reg(3)(3);
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romeaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(0)(4) &
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databuf_reg(1)(4) &
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databuf_reg(2)(4) &
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databuf_reg(3)(4);
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romeaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(0)(5) &
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databuf_reg(1)(5) &
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databuf_reg(2)(5) &
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databuf_reg(3)(5);
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romeaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(0)(6) &
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databuf_reg(1)(6) &
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databuf_reg(2)(6) &
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databuf_reg(3)(6);
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romeaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(0)(7) &
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databuf_reg(1)(7) &
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databuf_reg(2)(7) &
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databuf_reg(3)(7);
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romeaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(0)(8) &
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databuf_reg(1)(8) &
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databuf_reg(2)(8) &
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databuf_reg(3)(8);
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state_reg <= SUM;
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state_reg <= SUM;
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---------------------
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---------------------
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-- do distributed arithmetic sum on even part,
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-- do distributed arithmetic sum on even part,
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-- write even part to RAM
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-- write even part to RAM
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| Line 363... |
Line 294... |
ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg);
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ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg);
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col_reg <= col_reg + 1;
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col_reg <= col_reg + 1;
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col_tmp_reg <= col_reg + 2;
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col_tmp_reg <= col_reg + 2;
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romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(0) &
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databuf_reg(5)(0) &
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databuf_reg(6)(0) &
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databuf_reg(7)(0);
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romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(1) &
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databuf_reg(5)(1) &
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databuf_reg(6)(1) &
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databuf_reg(7)(1);
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romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(2) &
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databuf_reg(5)(2) &
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databuf_reg(6)(2) &
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databuf_reg(7)(2);
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romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(3) &
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databuf_reg(5)(3) &
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databuf_reg(6)(3) &
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databuf_reg(7)(3);
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romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(4) &
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databuf_reg(5)(4) &
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databuf_reg(6)(4) &
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databuf_reg(7)(4);
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romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(5) &
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databuf_reg(5)(5) &
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databuf_reg(6)(5) &
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databuf_reg(7)(5);
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romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(6) &
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databuf_reg(5)(6) &
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databuf_reg(6)(6) &
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databuf_reg(7)(6);
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romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(7) &
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databuf_reg(5)(7) &
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databuf_reg(6)(7) &
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databuf_reg(7)(7);
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romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(8) &
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databuf_reg(5)(8) &
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databuf_reg(6)(8) &
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databuf_reg(7)(8);
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state_reg <= WRITE_ODD;
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state_reg <= WRITE_ODD;
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---------------------
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---------------------
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-- do distributed arithmetic sum on odd part,
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-- do distributed arithmetic sum on odd part,
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-- write odd part to RAM
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-- write odd part to RAM
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| Line 437... |
Line 324... |
-- reverse col/row order for transposition purpose
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-- reverse col/row order for transposition purpose
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ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg);
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ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg);
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-- move to next column
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-- move to next column
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col_reg <= col_reg + 1;
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col_reg <= col_reg + 1;
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col_tmp_reg <= col_reg + 1;
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-- finished processing one input row
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-- finished processing one input row
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if col_reg = N - 1 then
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if col_reg = N - 1 then
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row_reg <= row_reg + 1;
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row_reg <= row_reg + 1;
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col_reg <= (others => '0');
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col_reg <= (others => '0');
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col_tmp_reg <= (others => '0');
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if row_reg = N - 1 then
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if row_reg = N - 1 then
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releasewr_reg <= '1';
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releasewr_reg <= '1';
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completed_reg <= '1';
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completed_reg <= '1';
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end if;
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end if;
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state_reg <= IDLE;
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state_reg <= IDLE;
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else
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else
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state_reg <= SUM;
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end if;
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--------------------------------
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-- OTHERS
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--------------------------------
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when others =>
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state_reg <= IDLE;
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end case;
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end if;
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end process;
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-- read precomputed MAC results from LUT
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-- read precomputed MAC results from LUT
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romeaddro0 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
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romeaddro0 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(0)(0) &
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databuf_reg(0)(0) &
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databuf_reg(1)(0) &
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databuf_reg(1)(0) &
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databuf_reg(2)(0) &
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databuf_reg(2)(0) &
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| Line 496... |
Line 397... |
databuf_reg(0)(8) &
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databuf_reg(0)(8) &
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databuf_reg(1)(8) &
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databuf_reg(1)(8) &
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databuf_reg(2)(8) &
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databuf_reg(2)(8) &
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databuf_reg(3)(8);
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databuf_reg(3)(8);
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state_reg <= SUM;
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end if;
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-- odd
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--------------------------------
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romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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-- OTHERS
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databuf_reg(4)(0) &
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--------------------------------
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databuf_reg(5)(0) &
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when others =>
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databuf_reg(6)(0) &
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state_reg <= IDLE;
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databuf_reg(7)(0);
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end case;
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romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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end if;
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databuf_reg(4)(1) &
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end process;
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databuf_reg(5)(1) &
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databuf_reg(6)(1) &
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databuf_reg(7)(1);
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romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(2) &
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databuf_reg(5)(2) &
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databuf_reg(6)(2) &
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databuf_reg(7)(2);
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romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(3) &
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databuf_reg(5)(3) &
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databuf_reg(6)(3) &
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databuf_reg(7)(3);
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romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(4) &
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databuf_reg(5)(4) &
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databuf_reg(6)(4) &
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databuf_reg(7)(4);
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romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(5) &
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databuf_reg(5)(5) &
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databuf_reg(6)(5) &
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databuf_reg(7)(5);
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romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(6) &
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databuf_reg(5)(6) &
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databuf_reg(6)(6) &
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databuf_reg(7)(6);
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romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(7) &
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databuf_reg(5)(7) &
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databuf_reg(6)(7) &
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databuf_reg(7)(7);
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romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
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databuf_reg(4)(8) &
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databuf_reg(5)(8) &
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databuf_reg(6)(8) &
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databuf_reg(7)(8);
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end RTL;
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end RTL;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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