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https://opencores.org/ocsvn/mdct/mdct/trunk
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| Rev 2 |
Rev 11 |
| Line 30... |
Line 30... |
use WORK.MDCT_PKG.all;
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use WORK.MDCT_PKG.all;
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entity ROME is
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entity ROME is
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port(
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port(
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addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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clk : in STD_LOGIC;
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datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
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datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
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);
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);
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end ROME;
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end ROME;
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std_logic_vector( CP+BM ),
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std_logic_vector( CP+BM ),
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std_logic_vector( BM ),
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std_logic_vector( BM ),
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std_logic_vector( CP ),
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std_logic_vector( CP ),
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(others => '0')
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(others => '0')
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);
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);
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signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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begin
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begin
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process( addr )
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datao <= rom( TO_INTEGER(UNSIGNED(addr_reg)) );
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process(clk)
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begin
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begin
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datao <= rom( TO_INTEGER(UNSIGNED(addr)) );
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if clk = '1' and clk'event then
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addr_reg <= addr;
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end if;
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end process;
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end process;
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end RTL;
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end RTL;
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