?rev1line? |
?rev2line? |
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; Copyright Mentor Graphics Corporation 2004
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;
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; All Rights Reserved.
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;
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; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
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; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
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;
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[Library]
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std = $MODEL_TECH/../std
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ieee = $MODEL_TECH/../ieee
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verilog = $MODEL_TECH/../verilog
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vital2000 = $MODEL_TECH/../vital2000
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std_developerskit = $MODEL_TECH/../std_developerskit
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synopsys = $MODEL_TECH/../synopsys
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modelsim_lib = $MODEL_TECH/../modelsim_lib
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;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
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;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
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work = work
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SIMPRIM = f:\Xilinx\vhdl\mti_se\simprim
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UNISIMS_VER = f:\Xilinx\verilog\mti_se\unisims_ver
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SIMPRIMS_VER = f:\Xilinx\verilog\mti_se\simprims_ver
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XILINXCORELIB_VER = f:\Xilinx\verilog\mti_se\XilinxCoreLib_ver
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UNISIM = f:\Xilinx\vhdl\mti_se\unisim
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XILINXCORELIB = f:\Xilinx\vhdl\mti_se\XilinxCoreLib
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[vcom]
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; VHDL93 variable selects language version as the default.
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; Default is VHDL-2002.
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; Value of 0 or 1987 for VHDL-1987.
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; Value of 1 or 1993 for VHDL-1993.
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; Default or value of 2 or 2002 for VHDL-2002.
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VHDL93 = 2002
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; Show source line containing error. Default is off.
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; Show_source = 1
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; Turn off unbound-component warnings. Default is on.
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; Show_Warning1 = 0
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; Turn off process-without-a-wait-statement warnings. Default is on.
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; Show_Warning2 = 0
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; Turn off null-range warnings. Default is on.
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; Show_Warning3 = 0
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; Turn off no-space-in-time-literal warnings. Default is on.
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; Show_Warning4 = 0
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; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
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; Show_Warning5 = 0
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; Turn off optimization for IEEE std_logic_1164 package. Default is on.
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; Optimize_1164 = 0
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; Turn on resolving of ambiguous function overloading in favor of the
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; "explicit" function declaration (not the one automatically created by
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; the compiler for each type declaration). Default is off.
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; The .ini file has Explict enabled so that std_logic_signed/unsigned
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; will match the behavior of synthesis tools.
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Explicit = 1
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; Turn off acceleration of the VITAL packages. Default is to accelerate.
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; NoVital = 1
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; Turn off VITAL compliance checking. Default is checking on.
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; NoVitalCheck = 1
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; Ignore VITAL compliance checking errors. Default is to not ignore.
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; IgnoreVitalErrors = 1
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; Turn off VITAL compliance checking warnings. Default is to show warnings.
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; Show_VitalChecksWarnings = 0
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; Turn off PSL assertion warning messges. Default is to show warnings.
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; Show_PslChecksWarnings = 0
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; Enable parsing of embedded PSL assertions. Default is enabled.
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; EmbeddedPsl = 0
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; Keep silent about case statement static warnings.
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; Default is to give a warning.
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; NoCaseStaticError = 1
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; Keep silent about warnings caused by aggregates that are not locally static.
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; Default is to give a warning.
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; NoOthersStaticError = 1
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; Treat as errors:
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; case statement static warnings
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; warnings caused by aggregates that are not locally static
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; Overrides NoCaseStaticError, NoOthersStaticError settings.
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; PedanticErrors = 1
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; Turn off inclusion of debugging info within design units.
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; Default is to include debugging info.
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; NoDebug = 1
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; Turn off "Loading..." messages. Default is messages on.
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; Quiet = 1
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; Turn on some limited synthesis rule compliance checking. Checks only:
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; -- signals used (read) by a process must be in the sensitivity list
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; CheckSynthesis = 1
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; Activate optimizations on expressions that do not involve signals,
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; waits, or function/procedure/task invocations. Default is off.
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; ScalarOpts = 1
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; Turns on lint-style checking.
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; Show_Lint = 1
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; Require the user to specify a configuration for all bindings,
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; and do not generate a compile time default binding for the
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; component. This will result in an elaboration error of
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; 'component not bound' if the user fails to do so. Avoids the rare
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; issue of a false dependency upon the unused default binding.
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; RequireConfigForAllDefaultBinding = 1
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; Peform default binding at compile time.
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; Default is to do default binding at load time.
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; BindAtCompile=1;
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; Inhibit range checking on subscripts of arrays. Range checking on
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; scalars defined with subtypes is inhibited by default.
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; NoIndexCheck = 1
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; Inhibit range checks on all (implicit and explicit) assignments to
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; scalar objects defined with subtypes.
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; NoRangeCheck = 1
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[vlog]
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; Turn off inclusion of debugging info within design units.
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; Default is to include debugging info.
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; NoDebug = 1
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; Turn on `protect compiler directive processing.
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; Default is to ignore `protect directives.
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; Protect = 1
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; Turn off "Loading..." messages. Default is messages on.
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; Quiet = 1
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; Turn on Verilog hazard checking (order-dependent accessing of global vars).
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; Default is off.
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; Hazard = 1
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; Turn on converting regular Verilog identifiers to uppercase. Allows case
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; insensitivity for module names. Default is no conversion.
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; UpCase = 1
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; Activate optimizations on expressions that do not involve signals,
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; waits, or function/procedure/task invocations. Default is off.
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; ScalarOpts = 1
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; Turns on lint-style checking.
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; Show_Lint = 1
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; Show source line containing error. Default is off.
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; Show_source = 1
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; Turn on bad option warning. Default is off.
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; Show_BadOptionWarning = 1
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; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
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vlog95compat = 0
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; Turn off PSL warning messges. Default is to show warnings.
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; Show_PslChecksWarnings = 0
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; Enable parsing of embedded PSL assertions. Default is enabled.
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; EmbeddedPsl = 0
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; Set the threshold for automatically identifying sparse Verilog memories.
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; A memory with depth equal to or more than the sparse memory threshold gets
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; marked as sparse automatically, unless specified otherwise in source code.
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; The default is 0 (i.e. no memory is automatically given sparse status)
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; SparseMemThreshold = 1048576
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; Set the maximum number of iterations permitted for a generate loop.
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; Restricting this permits the implementation to recognize infinite
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; generate loops.
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; GenerateLoopIterationMax = 100000
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; Set the maximum depth permitted for a recursive generate instantiation.
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; Restricting this permits the implementation to recognize infinite
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; recursions.
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; GenerateRecursionDepthMax = 200
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[sccom]
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; Enable use of SCV include files and library. Default is off.
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; UseScv = 1
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; Add C++ compiler options to the sccom command line by using this variable.
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; CppOptions = -g
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; Use custom C++ compiler located at this path rather than ModelSim default.
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; The path should point directly at a compiler executable.
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; CppPath = /usr/bin/g++
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; Enable verbose messages from sccom. Default is off.
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; SccomVerbose = 1
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; sccom logfile. Default is no logfile.
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; SccomLogfile = sccom.log
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[vsim]
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; vopt flow
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; Set to turn on automatic optimization of a design.
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; Default is off (pre-6.0 flow without vopt).
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; VoptFlow = 1
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; Simulator resolution
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; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
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resolution = 1ps
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; User time unit for run commands
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; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
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; unit specified for Resolution. For example, if Resolution is 100ps,
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; then UserTimeUnit defaults to ps.
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; Should generally be set to default.
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UserTimeUnit = default
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; Default run length
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RunLength = 0 ps
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; Maximum iterations that can be run without advancing simulation time
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IterationLimit = 5000
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; Contol PSL Assume during simulation
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; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
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; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
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; SimulateAssumeDirectives = 1
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; Directives to license manager can be set either as single value or as
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; space separated multi-values:
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; vhdl Immediately reserve a VHDL license
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; vlog Immediately reserve a Verilog license
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; plus Immediately reserve a VHDL and Verilog license
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; nomgc Do not look for Mentor Graphics Licenses
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; nomti Do not look for Model Technology Licenses
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; noqueue Do not wait in the license queue when a license is not available
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; viewsim Try for viewer license but accept simulator license(s) instead
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; of queuing for viewer license (PE ONLY)
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; Single value:
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; License = plus
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; Multi-value:
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; License = noqueue plus
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; Stop the simulator after a VHDL assertion message
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; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
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BreakOnAssertion = 3
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; VHDL assertion Message Format
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; %S - Severity Level
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; %R - Report Message
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; %T - Time of assertion
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; %D - Delta
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; %I - Instance or Region pathname (if available)
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; %i - Instance pathname with process
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; %O - Process name
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; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
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; %P - Instance or Region path without leaf process
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; %F - File
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; %L - Line number of assertion or, if assertion is in a subprogram, line
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; from which the call is made
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; %% - Print '%' character
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; If specific format for assertion level is defined, use its format.
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; If specific format is not define for assertion level, use AssertionFormatBreak
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; if assertion triggers a breakpoint (controlled by BreakOnAssertion level),
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; otherwise use AssertionFormat.
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;
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; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
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; AssertionFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
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; AssertionFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
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; AssertionFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
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; AssertionFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
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; AssertionFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
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; AssertionFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
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; Assertion File - alternate file for storing VHDL/PSL assertion messages
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; AssertFile = assert.log
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; Default radix for all windows and commands.
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; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
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DefaultRadix = symbolic
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; VSIM Startup command
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; Startup = do startup.do
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; File for saving command transcript
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TranscriptFile = transcript
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; File for saving command history
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; CommandHistory = cmdhist.log
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; Specify whether paths in simulator commands should be described
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; in VHDL or Verilog format.
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; For VHDL, PathSeparator = /
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; For Verilog, PathSeparator = .
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; Must not be the same character as DatasetSeparator.
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PathSeparator = /
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; Specify the dataset separator for fully rooted contexts.
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; The default is ':'. For example: sim:/top
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; Must not be the same character as PathSeparator.
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DatasetSeparator = :
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; Disable VHDL assertion messages
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; IgnoreNote = 1
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; IgnoreWarning = 1
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; IgnoreError = 1
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; IgnoreFailure = 1
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; Default force kind. May be freeze, drive, or deposit
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; or in other terms, fixed, wired, or charged.
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; DefaultForceKind = freeze
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; If zero, open files when elaborated; otherwise, open files on
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; first read or write. Default is 0.
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; DelayFileOpen = 1
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; Control VHDL files opened for write.
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; 0 = Buffered, 1 = Unbuffered
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UnbufferedOutput = 0
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; Control the number of VHDL files open concurrently.
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; This number should always be less than the current ulimit
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; setting for max file descriptors.
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; 0 = unlimited
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ConcurrentFileLimit = 40
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; Control the number of hierarchical regions displayed as
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; part of a signal name shown in the Wave window.
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; A value of zero tells VSIM to display the full name.
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; The default is 0.
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; WaveSignalNameWidth = 0
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; Turn off warnings from the std_logic_arith, std_logic_unsigned
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; and std_logic_signed packages.
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; StdArithNoWarnings = 1
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; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
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; NumericStdNoWarnings = 1
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; Control the format of a generate statement label. Do not quote it.
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; GenerateFormat = %s__%d
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; Specify whether checkpoint files should be compressed.
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; The default is 1 (compressed).
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; CheckpointCompressMode = 0
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; List of dynamically loaded objects for Verilog PLI applications
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; Veriuser = veriuser.sl
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; Specify default options for the restart command. Options can be one
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; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
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; DefaultRestartOptions = -force
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; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
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; (> 500 megabyte memory footprint). Default is disabled.
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; Specify number of megabytes to lock.
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; LockedMemory = 1000
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; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading.
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; This is necessary when C++ files have been compiled with aCC's -AA option.
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; The default behavior is to use /usr/lib/libCsup.sl.
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; UseCsupV2 = 1
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; Turn on (1) or off (0) WLF file compression.
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; The default is 1 (compress WLF file).
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; WLFCompress = 0
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; Specify whether to save all design hierarchy (1) in the WLF file
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; or only regions containing logged signals (0).
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; The default is 0 (log only regions with logged signals).
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; WLFSaveAllRegions = 1
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; WLF file time limit. Limit WLF file by time, as closely as possible,
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; to the specified amount of simulation time. When the limit is exceeded
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; the earliest times get truncated from the file.
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; If both time and size limits are specified the most restrictive is used.
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; UserTimeUnits are used if time units are not specified.
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; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
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; WLFTimeLimit = 0
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; WLF file size limit. Limit WLF file size, as closely as possible,
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; to the specified number of megabytes. If both time and size limits
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; are specified then the most restrictive is used.
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; The default is 0 (no limit).
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; WLFSizeLimit = 1000
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; Specify whether or not a WLF file should be deleted when the
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; simulation ends. A value of 1 will cause the WLF file to be deleted.
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; The default is 0 (do not delete WLF file when simulation ends).
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; WLFDeleteOnQuit = 1
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; Specify whether or not a WLF file should be optimized during
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; simulation. If set to 0, the WLF file will not be optimized.
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; The default is 1, optimize the WLF file.
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; WLFOptimize = 0
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; Specify the name of the WLF file.
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; The default is vsim.wlf
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; WLFFilename = vsim.wlf
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; Specify the WLF file event collapse mode.
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; 0 = Preserve all events and event order. (same as -wlfnocollapse)
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; 1 = Only record values of logged objects at the end of a simulator iteration.
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; (same as -wlfcollapsedelta)
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; 2 = Only record values of logged objects at the end of a simulator time step.
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; (same as -wlfcollapsetime)
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; The default is 1.
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; WLFCollapseMode = 0
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; Specify whether or not integer arrays will appear as memories.
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; The default is 1 (display integer arrays as memories).
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; ShowIntMem = 0
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; Specify whether or not enumerated type arrays (other than std_logic-based)
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; will appear as memories.
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; The default is 1 (display enumerated type arrays as memories).
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; ShowEnumMem = 0
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; Specify whether or not arrays of 3 or more dimensions will appear as memories.
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; The default is 1 (display 3D+ type arrays as memories).
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; Show3DMem = 0
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; Turn on/off undebuggable SystemC type warnings. Default is on.
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; ShowUndebuggableScTypeWarning = 0
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; Turn on/off unassociated SystemC name warnings. Default is off.
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; ShowUnassociatedScNameWarning = 1
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; Turn on/off PSL assertion pass enable. Default is off.
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; AssertionPassEnable = 1
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; Turn on/off PSL assertion fail enable. Default is on.
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; AssertionFailEnable = 0
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; Set PSL assertion pass limit. Default is 1.
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; Any positive integer, -1 for infinity.
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; AssertionPassLimit = -1
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; Set PSL assertion fail limit. Default is 1.
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; Any positive integer, -1 for infinity.
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; AssertionFailLimit = -1
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; Turn on/off PSL assertion pass log. Default is on.
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; AssertionPassLog = 0
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; Turn on/off PSL assertion fail log. Default is on.
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; AssertionFailLog = 0
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; Set action type for PSL assertion fail action. Default is continue.
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; 0 = Continue 1 = Break 2 = Exit
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; AssertionFailAction = 1
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; Turn on/off all PSL cover directive enables. Default is on.
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; CoverEnable = 0
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; Turn on/off PSL cover log. Default is off.
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; CoverLog = 1
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; Set "at_least" value for all PSL cover directives. Default is 1.
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; CoverAtLeast = 2
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; Set weight for all PSL cover directives. Default is 1.
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; CoverWeight = 2
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; Check vsim plusargs. Default is 0 (off).
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; 0 = Don't check plusargs
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; 1 = Warning on unrecognized plusarg
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; 2 = Error and exit on unrecognized plusarg
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; CheckPlusargs = 1
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|
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; Load the specified shared objects with the RTLD_GLOBAL flag.
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; This gives global visibility to all symbols in the shared objects,
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; meaning that subsequently loaded shared objects can bind to symbols
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; in the global shared objects. The list of shared objects should
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; be whitespace delimited. This option is not supported on the
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; Windows or AIX platforms.
|
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; GlobalSharedObjectList = example1.so example2.so example3.so
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[lmc]
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; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
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libsm = $MODEL_TECH/libsm.sl
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; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
|
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; libsm = $MODEL_TECH/libsm.dll
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; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
|
|
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
|
|
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
|
|
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
|
|
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
|
|
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
|
|
; Logic Modeling's SmartModel SWIFT software (Windows NT)
|
|
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
|
|
; Logic Modeling's SmartModel SWIFT software (Linux)
|
|
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
|
|
|
|
; ModelSim's interface to Logic Modeling's hardware modeler SFI software
|
|
libhm = $MODEL_TECH/libhm.sl
|
|
; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
|
|
; libhm = $MODEL_TECH/libhm.dll
|
|
; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
|
|
; libsfi = /lib/hp700/libsfi.sl
|
|
; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
|
|
; libsfi = /lib/rs6000/libsfi.a
|
|
; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
|
|
; libsfi = /lib/sun4.solaris/libsfi.so
|
|
; Logic Modeling's hardware modeler SFI software (Windows NT)
|
|
; libsfi = /lib/pcnt/lm_sfi.dll
|
|
; Logic Modeling's hardware modeler SFI software (Linux)
|
|
; libsfi = /lib/linux/libsfi.so
|
|
|
|
[msg_system]
|
|
; Change a message severity or suppress a message.
|
|
; The format is: = [,...]
|
|
; Examples:
|
|
; note = 3009
|
|
; warning = 3033
|
|
; error = 3010,3016
|
|
; suppress = 3009,3016,3043
|
|
; The command verror can be used to get the complete
|
|
; description of a message.
|
|
|
|
[Project]
|
|
Project_Version = 6
|
|
Project_DefaultLib = work
|
|
Project_SortMethod = unused
|
|
Project_Files_Count = 24
|
|
Project_File_0 = C:/elektronika/dct/MDCT/source/xilinx/RAM.VHD
|
|
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 17 dont_compile 0 cover_nosub 0 vhdl_use93 2002
|
|
Project_File_1 = C:/elektronika/dct/mdct/source/ROME.VHD
|
|
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144870599 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
|
Project_File_2 = C:/elektronika/dct/MDCT/source/DBUFCTL.VHD
|
|
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SOURCE last_compile 1143785621 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002
|
|
Project_File_3 = C:/elektronika/dct/mdct/source/testbench/MDCT_TB.DO
|
|
Project_File_P_3 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
|
|
Project_File_4 = C:/elektronika/dct/MDCT/source/xilinx/ROME.VHD
|
|
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002
|
|
Project_File_5 = C:/elektronika/dct/mdct/source/testbench/RUNSIM.DO
|
|
Project_File_P_5 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
|
|
Project_File_6 = C:/elektronika/dct/MDCT/source/testbench/COMPILE_TIMING.DO
|
|
Project_File_P_6 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
|
|
Project_File_7 = C:/elektronika/dct/mdct/source/RAM.VHD
|
|
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143489389 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
|
Project_File_8 = C:/elektronika/dct/MDCT/source/DCT2D.VHD
|
|
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SOURCE last_compile 1143972066 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 87
|
|
Project_File_9 = C:/elektronika/dct/mdct/source/testbench/CLKGEN.VHD
|
|
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143489388 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
|
Project_File_10 = C:/elektronika/dct/MDCT/source/xilinx/romo_xil.vhd
|
|
Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002
|
|
Project_File_11 = C:/elektronika/dct/mdct/source/testbench/MDCT_TB.VHD
|
|
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1144881653 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
|
Project_File_12 = C:/elektronika/dct/MDCT/synthesis/mdct_temp_2/MDCT_out.vhd
|
|
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder PAR last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002
|
|
Project_File_13 = C:/elektronika/dct/MDCT/source/testbench/RUNSIM_TIMING.DO
|
|
Project_File_P_13 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
|
|
Project_File_14 = C:/elektronika/dct/mdct/source/ROMO.VHD
|
|
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145568090 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
|
Project_File_15 = C:/elektronika/dct/mdct/source/testbench/MDCTTB_PKG.vhd
|
|
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143976585 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
|
Project_File_16 = C:/elektronika/dct/MDCT/source/xilinx/ram_xil.vhd
|
|
Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 18 dont_compile 0 cover_nosub 0 vhdl_use93 2002
|
|
Project_File_17 = C:/elektronika/dct/MDCT/source/xilinx/ROMO.VHD
|
|
Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002
|
|
Project_File_18 = C:/elektronika/dct/mdct/source/MDCT.VHD
|
|
Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143931873 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
|
Project_File_19 = C:/elektronika/dct/mdct/source/DCT1D.vhd
|
|
Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145135163 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
|
Project_File_20 = C:/elektronika/dct/mdct/source/testbench/INPIMAGE.VHD
|
|
Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143979283 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
|
Project_File_21 = C:/elektronika/dct/mdct/source/MDCT_PKG.vhd
|
|
Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144447956 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
|
Project_File_22 = C:/elektronika/dct/MDCT/source/testbench/random1.vhd
|
|
Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder TESTBENCH last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002
|
|
Project_File_23 = C:/elektronika/dct/MDCT/source/xilinx/rome_xil.vhd
|
|
Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002
|
|
Project_Sim_Count = 0
|
|
Project_Folder_Count = 5
|
|
Project_Folder_0 = XILINX
|
|
Project_Folder_P_0 = folder SOURCE
|
|
Project_Folder_1 = TESTBENCH
|
|
Project_Folder_P_1 = folder SOURCE
|
|
Project_Folder_2 = SOURCE
|
|
Project_Folder_P_2 = folder {Top Level}
|
|
Project_Folder_3 = MODELSIM
|
|
Project_Folder_P_3 = folder {Top Level}
|
|
Project_Folder_4 = PAR
|
|
Project_Folder_P_4 = folder {Top Level}
|
|
Echo_Compile_Output = 0
|
|
Save_Compile_Report = 1
|
|
Project_Opt_Count = 0
|
|
ForceSoftPaths = 1
|
|
ReOpenSourceFiles = 1
|
|
VERILOG_DoubleClick = Edit
|
|
VERILOG_CustomDoubleClick =
|
|
VHDL_DoubleClick = Edit
|
|
VHDL_CustomDoubleClick =
|
|
PSL_DoubleClick = Edit
|
|
PSL_CustomDoubleClick =
|
|
TEXT_DoubleClick = Edit
|
|
TEXT_CustomDoubleClick =
|
|
SYSTEMC_DoubleClick = Edit
|
|
SYSTEMC_CustomDoubleClick =
|
|
TCL_DoubleClick = Edit
|
|
TCL_CustomDoubleClick =
|
|
MACRO_DoubleClick = Edit
|
|
MACRO_CustomDoubleClick =
|
|
VCD_DoubleClick = Edit
|
|
VCD_CustomDoubleClick =
|
|
SDF_DoubleClick = Edit
|
|
SDF_CustomDoubleClick =
|
|
XML_DoubleClick = Edit
|
|
XML_CustomDoubleClick =
|
|
LOGFILE_DoubleClick = Edit
|
|
LOGFILE_CustomDoubleClick =
|
|
EditorState = {tabbed horizontal 1} {C:/elektronika/dct/MDCT/source/DCT1D.vhd 0 0} {C:/elektronika/dct/MDCT/source/testbench/INPIMAGE.VHD 0 0} {F:/Xilinx/vhdl/src/simprims/simprim_VITAL_mti.vhd 0 0} {C:/elektronika/dct/MDCT/source/testbench/MDCTTB_PKG.vhd 0 1}
|
|
Project_Major_Version = 6
|
|
Project_Minor_Version = 1
|
