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; Copyright Mentor Graphics Corporation 2004
 
;
 
; All Rights Reserved.
 
;
 
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
 
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
 
;
 
 
 
[Library]
 
std = $MODEL_TECH/../std
 
ieee = $MODEL_TECH/../ieee
 
verilog = $MODEL_TECH/../verilog
 
vital2000 = $MODEL_TECH/../vital2000
 
std_developerskit = $MODEL_TECH/../std_developerskit
 
synopsys = $MODEL_TECH/../synopsys
 
modelsim_lib = $MODEL_TECH/../modelsim_lib
 
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers       // Source files only for this release
 
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
 
 
 
work = work
 
SIMPRIM = f:\Xilinx\vhdl\mti_se\simprim
 
UNISIMS_VER = f:\Xilinx\verilog\mti_se\unisims_ver
 
SIMPRIMS_VER = f:\Xilinx\verilog\mti_se\simprims_ver
 
XILINXCORELIB_VER = f:\Xilinx\verilog\mti_se\XilinxCoreLib_ver
 
UNISIM = f:\Xilinx\vhdl\mti_se\unisim
 
XILINXCORELIB = f:\Xilinx\vhdl\mti_se\XilinxCoreLib
 
[vcom]
 
; VHDL93 variable selects language version as the default.
 
; Default is VHDL-2002.
 
; Value of 0 or 1987 for VHDL-1987.
 
; Value of 1 or 1993 for VHDL-1993.
 
; Default or value of 2 or 2002 for VHDL-2002.
 
VHDL93 = 2002
 
 
 
; Show source line containing error. Default is off.
 
; Show_source = 1
 
 
 
; Turn off unbound-component warnings. Default is on.
 
; Show_Warning1 = 0
 
 
 
; Turn off process-without-a-wait-statement warnings. Default is on.
 
; Show_Warning2 = 0
 
 
 
; Turn off null-range warnings. Default is on.
 
; Show_Warning3 = 0
 
 
 
; Turn off no-space-in-time-literal warnings. Default is on.
 
; Show_Warning4 = 0
 
 
 
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
 
; Show_Warning5 = 0
 
 
 
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
 
; Optimize_1164 = 0
 
 
 
; Turn on resolving of ambiguous function overloading in favor of the
 
; "explicit" function declaration (not the one automatically created by
 
; the compiler for each type declaration). Default is off.
 
; The .ini file has Explict enabled so that std_logic_signed/unsigned
 
; will match the behavior of synthesis tools.
 
Explicit = 1
 
 
 
; Turn off acceleration of the VITAL packages. Default is to accelerate.
 
; NoVital = 1
 
 
 
; Turn off VITAL compliance checking. Default is checking on.
 
; NoVitalCheck = 1
 
 
 
; Ignore VITAL compliance checking errors. Default is to not ignore.
 
; IgnoreVitalErrors = 1
 
 
 
; Turn off VITAL compliance checking warnings. Default is to show warnings.
 
; Show_VitalChecksWarnings = 0
 
 
 
; Turn off PSL assertion warning messges. Default is to show warnings.
 
; Show_PslChecksWarnings = 0
 
 
 
; Enable parsing of embedded PSL assertions. Default is enabled.
 
; EmbeddedPsl = 0
 
 
 
; Keep silent about case statement static warnings.
 
; Default is to give a warning.
 
; NoCaseStaticError = 1
 
 
 
; Keep silent about warnings caused by aggregates that are not locally static.
 
; Default is to give a warning.
 
; NoOthersStaticError = 1
 
 
 
; Treat as errors:
 
;   case statement static warnings
 
;   warnings caused by aggregates that are not locally static
 
; Overrides NoCaseStaticError, NoOthersStaticError settings.
 
; PedanticErrors = 1
 
 
 
; Turn off inclusion of debugging info within design units.
 
; Default is to include debugging info.
 
; NoDebug = 1
 
 
 
; Turn off "Loading..." messages. Default is messages on.
 
; Quiet = 1
 
 
 
; Turn on some limited synthesis rule compliance checking. Checks only:
 
;    -- signals used (read) by a process must be in the sensitivity list
 
; CheckSynthesis = 1
 
 
 
; Activate optimizations on expressions that do not involve signals,
 
; waits, or function/procedure/task invocations. Default is off.
 
; ScalarOpts = 1
 
 
 
; Turns on lint-style checking.
 
; Show_Lint = 1
 
 
 
; Require the user to specify a configuration for all bindings,
 
; and do not generate a compile time default binding for the
 
; component. This will result in an elaboration error of
 
; 'component not bound' if the user fails to do so. Avoids the rare
 
; issue of a false dependency upon the unused default binding.
 
; RequireConfigForAllDefaultBinding = 1
 
 
 
; Peform default binding at compile time.
 
; Default is to do default binding at load time.
 
; BindAtCompile=1;
 
 
 
; Inhibit range checking on subscripts of arrays. Range checking on
 
; scalars defined with subtypes is inhibited by default.
 
; NoIndexCheck = 1
 
 
 
; Inhibit range checks on all (implicit and explicit) assignments to
 
; scalar objects defined with subtypes.
 
; NoRangeCheck = 1
 
 
 
[vlog]
 
 
 
; Turn off inclusion of debugging info within design units.
 
; Default is to include debugging info.
 
; NoDebug = 1
 
 
 
; Turn on `protect compiler directive processing.
 
; Default is to ignore `protect directives.
 
; Protect = 1
 
 
 
; Turn off "Loading..." messages. Default is messages on.
 
; Quiet = 1
 
 
 
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
 
; Default is off.
 
; Hazard = 1
 
 
 
; Turn on converting regular Verilog identifiers to uppercase. Allows case
 
; insensitivity for module names. Default is no conversion.
 
; UpCase = 1
 
 
 
; Activate optimizations on expressions that do not involve signals,
 
; waits, or function/procedure/task invocations. Default is off.
 
; ScalarOpts = 1
 
 
 
; Turns on lint-style checking.
 
; Show_Lint = 1
 
 
 
; Show source line containing error. Default is off.
 
; Show_source = 1
 
 
 
; Turn on bad option warning. Default is off.
 
; Show_BadOptionWarning = 1
 
 
 
; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
 
vlog95compat = 0
 
 
 
; Turn off PSL warning messges. Default is to show warnings.
 
; Show_PslChecksWarnings = 0
 
 
 
; Enable parsing of embedded PSL assertions. Default is enabled.
 
; EmbeddedPsl = 0
 
 
 
; Set the threshold for automatically identifying sparse Verilog memories.
 
; A memory with depth equal to or more than the sparse memory threshold gets
 
; marked as sparse automatically, unless specified otherwise in source code.
 
; The default is 0 (i.e. no memory is automatically given sparse status)
 
; SparseMemThreshold = 1048576
 
 
 
; Set the maximum number of iterations permitted for a generate loop.
 
; Restricting this permits the implementation to recognize infinite
 
; generate loops.
 
; GenerateLoopIterationMax = 100000
 
 
 
; Set the maximum depth permitted for a recursive generate instantiation.
 
; Restricting this permits the implementation to recognize infinite
 
; recursions.
 
; GenerateRecursionDepthMax = 200
 
 
 
 
 
[sccom]
 
; Enable use of SCV include files and library.  Default is off.
 
; UseScv = 1
 
 
 
; Add C++ compiler options to the sccom command line by using this variable.
 
; CppOptions = -g
 
 
 
; Use custom C++ compiler located at this path rather than ModelSim default.
 
; The path should point directly at a compiler executable.
 
; CppPath = /usr/bin/g++
 
 
 
; Enable verbose messages from sccom.  Default is off.
 
; SccomVerbose = 1
 
 
 
; sccom logfile.  Default is no logfile.
 
; SccomLogfile = sccom.log
 
 
 
[vsim]
 
 
 
; vopt flow
 
; Set to turn on automatic optimization of a design.
 
; Default is off (pre-6.0 flow without vopt).
 
; VoptFlow = 1
 
 
 
; Simulator resolution
 
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
 
resolution = 1ps
 
 
 
; User time unit for run commands
 
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
 
; unit specified for Resolution. For example, if Resolution is 100ps,
 
; then UserTimeUnit defaults to ps.
 
; Should generally be set to default.
 
UserTimeUnit = default
 
 
 
; Default run length
 
RunLength = 0 ps
 
 
 
; Maximum iterations that can be run without advancing simulation time
 
IterationLimit = 5000
 
 
 
; Contol PSL Assume during simulation
 
; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
 
; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
 
; SimulateAssumeDirectives = 1
 
 
 
; Directives to license manager can be set either as single value or as
 
; space separated multi-values:
 
; vhdl          Immediately reserve a VHDL license
 
; vlog          Immediately reserve a Verilog license
 
; plus          Immediately reserve a VHDL and Verilog license
 
; nomgc         Do not look for Mentor Graphics Licenses
 
; nomti         Do not look for Model Technology Licenses
 
; noqueue       Do not wait in the license queue when a license is not available
 
; viewsim       Try for viewer license but accept simulator license(s) instead
 
;               of queuing for viewer license (PE ONLY)
 
; Single value:
 
; License = plus
 
; Multi-value:
 
; License = noqueue plus
 
 
 
; Stop the simulator after a VHDL assertion message
 
; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
 
BreakOnAssertion = 3
 
 
 
; VHDL assertion Message Format
 
; %S - Severity Level
 
; %R - Report Message
 
; %T - Time of assertion
 
; %D - Delta
 
; %I - Instance or Region pathname (if available)
 
; %i - Instance pathname with process
 
; %O - Process name
 
; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
 
; %P - Instance or Region path without leaf process
 
; %F - File
 
; %L - Line number of assertion or, if assertion is in a subprogram, line
 
;      from which the call is made
 
; %% - Print '%' character
 
; If specific format for assertion level is defined, use its format.
 
; If specific format is not define for assertion level, use AssertionFormatBreak
 
; if assertion triggers a breakpoint (controlled by BreakOnAssertion level),
 
; otherwise use AssertionFormat.
 
;
 
; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
 
; AssertionFormatBreak   = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
 
; AssertionFormatNote    = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
 
; AssertionFormatWarning = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
 
; AssertionFormatError   = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
 
; AssertionFormatFail    = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
 
; AssertionFormatFatal  = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
 
 
 
; Assertion File - alternate file for storing VHDL/PSL assertion messages
 
; AssertFile = assert.log
 
 
 
; Default radix for all windows and commands.
 
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
 
DefaultRadix = symbolic
 
 
 
; VSIM Startup command
 
; Startup = do startup.do
 
 
 
; File for saving command transcript
 
TranscriptFile = transcript
 
 
 
; File for saving command history
 
; CommandHistory = cmdhist.log
 
 
 
; Specify whether paths in simulator commands should be described
 
; in VHDL or Verilog format.
 
; For VHDL, PathSeparator = /
 
; For Verilog, PathSeparator = .
 
; Must not be the same character as DatasetSeparator.
 
PathSeparator = /
 
 
 
; Specify the dataset separator for fully rooted contexts.
 
; The default is ':'. For example: sim:/top
 
; Must not be the same character as PathSeparator.
 
DatasetSeparator = :
 
 
 
; Disable VHDL assertion messages
 
; IgnoreNote = 1
 
; IgnoreWarning = 1
 
; IgnoreError = 1
 
; IgnoreFailure = 1
 
 
 
; Default force kind. May be freeze, drive, or deposit
 
; or in other terms, fixed, wired, or charged.
 
; DefaultForceKind = freeze
 
 
 
; If zero, open files when elaborated; otherwise, open files on
 
; first read or write.  Default is 0.
 
; DelayFileOpen = 1
 
 
 
; Control VHDL files opened for write.
 
;   0 = Buffered, 1 = Unbuffered
 
UnbufferedOutput = 0
 
 
 
; Control the number of VHDL files open concurrently.
 
; This number should always be less than the current ulimit
 
; setting for max file descriptors.
 
;   0 = unlimited
 
ConcurrentFileLimit = 40
 
 
 
; Control the number of hierarchical regions displayed as
 
; part of a signal name shown in the Wave window.
 
; A value of zero tells VSIM to display the full name.
 
; The default is 0.
 
; WaveSignalNameWidth = 0
 
 
 
; Turn off warnings from the std_logic_arith, std_logic_unsigned
 
; and std_logic_signed packages.
 
; StdArithNoWarnings = 1
 
 
 
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
 
; NumericStdNoWarnings = 1
 
 
 
; Control the format of a generate statement label. Do not quote it.
 
; GenerateFormat = %s__%d
 
 
 
; Specify whether checkpoint files should be compressed.
 
; The default is 1 (compressed).
 
; CheckpointCompressMode = 0
 
 
 
; List of dynamically loaded objects for Verilog PLI applications
 
; Veriuser = veriuser.sl
 
 
 
; Specify default options for the restart command. Options can be one
 
; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
 
; DefaultRestartOptions = -force
 
 
 
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
 
; (> 500 megabyte memory footprint). Default is disabled.
 
; Specify number of megabytes to lock.
 
; LockedMemory = 1000
 
 
 
; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading.
 
; This is necessary when C++ files have been compiled with aCC's -AA option.
 
; The default behavior is to use /usr/lib/libCsup.sl.
 
; UseCsupV2 = 1
 
 
 
; Turn on (1) or off (0) WLF file compression.
 
; The default is 1 (compress WLF file).
 
; WLFCompress = 0
 
 
 
; Specify whether to save all design hierarchy (1) in the WLF file
 
; or only regions containing logged signals (0).
 
; The default is 0 (log only regions with logged signals).
 
; WLFSaveAllRegions = 1
 
 
 
; WLF file time limit.  Limit WLF file by time, as closely as possible,
 
; to the specified amount of simulation time.  When the limit is exceeded
 
; the earliest times get truncated from the file.
 
; If both time and size limits are specified the most restrictive is used.
 
; UserTimeUnits are used if time units are not specified.
 
; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
 
; WLFTimeLimit = 0
 
 
 
; WLF file size limit.  Limit WLF file size, as closely as possible,
 
; to the specified number of megabytes.  If both time and size limits
 
; are specified then the most restrictive is used.
 
; The default is 0 (no limit).
 
; WLFSizeLimit = 1000
 
 
 
; Specify whether or not a WLF file should be deleted when the
 
; simulation ends.  A value of 1 will cause the WLF file to be deleted.
 
; The default is 0 (do not delete WLF file when simulation ends).
 
; WLFDeleteOnQuit = 1
 
 
 
; Specify whether or not a WLF file should be optimized during
 
; simulation.  If set to 0, the WLF file will not be optimized.
 
; The default is 1, optimize the WLF file.
 
; WLFOptimize = 0
 
 
 
; Specify the name of the WLF file.
 
; The default is vsim.wlf
 
; WLFFilename = vsim.wlf
 
 
 
; Specify the WLF file event collapse mode.
 
; 0 = Preserve all events and event order. (same as -wlfnocollapse)
 
; 1 = Only record values of logged objects at the end of a simulator iteration.
 
;     (same as -wlfcollapsedelta)
 
; 2 = Only record values of logged objects at the end of a simulator time step.
 
;     (same as -wlfcollapsetime)
 
; The default is 1.
 
; WLFCollapseMode = 0
 
 
 
; Specify whether or not integer arrays will appear as memories.
 
; The default is 1 (display integer arrays as memories).
 
; ShowIntMem = 0
 
 
 
; Specify whether or not enumerated type arrays (other than std_logic-based)
 
; will appear as memories.
 
; The default is 1 (display enumerated type arrays as memories).
 
; ShowEnumMem = 0
 
 
 
; Specify whether or not arrays of 3 or more dimensions will appear as memories.
 
; The default is 1 (display 3D+ type arrays as memories).
 
; Show3DMem = 0
 
 
 
; Turn on/off undebuggable SystemC type warnings. Default is on.
 
; ShowUndebuggableScTypeWarning = 0
 
 
 
; Turn on/off unassociated SystemC name warnings. Default is off.
 
; ShowUnassociatedScNameWarning = 1
 
 
 
; Turn on/off PSL assertion pass enable. Default is off.
 
; AssertionPassEnable = 1
 
 
 
; Turn on/off PSL assertion fail enable. Default is on.
 
; AssertionFailEnable = 0
 
 
 
; Set PSL assertion pass limit. Default is 1.
 
; Any positive integer, -1 for infinity.
 
; AssertionPassLimit = -1
 
 
 
; Set PSL assertion fail limit. Default is 1.
 
; Any positive integer, -1 for infinity.
 
; AssertionFailLimit = -1
 
 
 
; Turn on/off PSL assertion pass log. Default is on.
 
; AssertionPassLog = 0
 
 
 
; Turn on/off PSL assertion fail log. Default is on.
 
; AssertionFailLog = 0
 
 
 
; Set action type for PSL assertion fail action. Default is continue.
 
; 0 = Continue  1 = Break  2 = Exit
 
; AssertionFailAction = 1
 
 
 
; Turn on/off all PSL cover directive enables.  Default is on.
 
; CoverEnable = 0
 
 
 
; Turn on/off PSL cover log.  Default is off.
 
; CoverLog = 1
 
 
 
; Set "at_least" value for all PSL cover directives.  Default is 1.
 
; CoverAtLeast = 2
 
 
 
; Set weight for all PSL cover directives.  Default is 1.
 
; CoverWeight = 2
 
 
 
; Check vsim plusargs.  Default is 0 (off).
 
; 0 = Don't check plusargs
 
; 1 = Warning on unrecognized plusarg
 
; 2 = Error and exit on unrecognized plusarg
 
; CheckPlusargs = 1
 
 
 
; Load the specified shared objects with the RTLD_GLOBAL flag.
 
; This gives global visibility to all symbols in the shared objects,
 
; meaning that subsequently loaded shared objects can bind to symbols
 
; in the global shared objects.  The list of shared objects should
 
; be whitespace delimited.  This option is not supported on the
 
; Windows or AIX platforms.
 
; GlobalSharedObjectList = example1.so example2.so example3.so
 
 
 
[lmc]
 
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
 
libsm = $MODEL_TECH/libsm.sl
 
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
 
; libsm = $MODEL_TECH/libsm.dll
 
;  Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
 
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
 
;  Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
 
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
 
;  Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
 
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
 
;  Logic Modeling's SmartModel SWIFT software (Windows NT)
 
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
 
;  Logic Modeling's SmartModel SWIFT software (Linux)
 
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
 
 
 
; ModelSim's interface to Logic Modeling's hardware modeler SFI software
 
libhm = $MODEL_TECH/libhm.sl
 
; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
 
; libhm = $MODEL_TECH/libhm.dll
 
;  Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
 
; libsfi = /lib/hp700/libsfi.sl
 
;  Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
 
; libsfi = /lib/rs6000/libsfi.a
 
;  Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
 
; libsfi = /lib/sun4.solaris/libsfi.so
 
;  Logic Modeling's hardware modeler SFI software (Windows NT)
 
; libsfi = /lib/pcnt/lm_sfi.dll
 
;  Logic Modeling's hardware modeler SFI software (Linux)
 
; libsfi = /lib/linux/libsfi.so
 
 
 
[msg_system]
 
; Change a message severity or suppress a message.
 
; The format is:  = [,...]
 
; Examples:
 
;   note = 3009
 
;   warning = 3033
 
;   error = 3010,3016
 
;   suppress = 3009,3016,3043
 
; The command verror  can be used to get the complete
 
; description of a message.
 
 
 
[Project]
 
Project_Version = 6
 
Project_DefaultLib = work
 
Project_SortMethod = unused
 
Project_Files_Count = 24
 
Project_File_0 = C:/elektronika/dct/MDCT/source/xilinx/RAM.VHD
 
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 17 dont_compile 0 cover_nosub 0 vhdl_use93 2002
 
Project_File_1 = C:/elektronika/dct/mdct/source/ROME.VHD
 
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144870599 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 93
 
Project_File_2 = C:/elektronika/dct/MDCT/source/DBUFCTL.VHD
 
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SOURCE last_compile 1143785621 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 
Project_File_3 = C:/elektronika/dct/mdct/source/testbench/MDCT_TB.DO
 
Project_File_P_3 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
 
Project_File_4 = C:/elektronika/dct/MDCT/source/xilinx/ROME.VHD
 
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 
Project_File_5 = C:/elektronika/dct/mdct/source/testbench/RUNSIM.DO
 
Project_File_P_5 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
 
Project_File_6 = C:/elektronika/dct/MDCT/source/testbench/COMPILE_TIMING.DO
 
Project_File_P_6 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
 
Project_File_7 = C:/elektronika/dct/mdct/source/RAM.VHD
 
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143489389 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 93
 
Project_File_8 = C:/elektronika/dct/MDCT/source/DCT2D.VHD
 
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SOURCE last_compile 1143972066 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 87
 
Project_File_9 = C:/elektronika/dct/mdct/source/testbench/CLKGEN.VHD
 
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143489388 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 93
 
Project_File_10 = C:/elektronika/dct/MDCT/source/xilinx/romo_xil.vhd
 
Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 
Project_File_11 = C:/elektronika/dct/mdct/source/testbench/MDCT_TB.VHD
 
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1144881653 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 93
 
Project_File_12 = C:/elektronika/dct/MDCT/synthesis/mdct_temp_2/MDCT_out.vhd
 
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder PAR last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 
Project_File_13 = C:/elektronika/dct/MDCT/source/testbench/RUNSIM_TIMING.DO
 
Project_File_P_13 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002
 
Project_File_14 = C:/elektronika/dct/mdct/source/ROMO.VHD
 
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145568090 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 93
 
Project_File_15 = C:/elektronika/dct/mdct/source/testbench/MDCTTB_PKG.vhd
 
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143976585 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 93
 
Project_File_16 = C:/elektronika/dct/MDCT/source/xilinx/ram_xil.vhd
 
Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 18 dont_compile 0 cover_nosub 0 vhdl_use93 2002
 
Project_File_17 = C:/elektronika/dct/MDCT/source/xilinx/ROMO.VHD
 
Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 
Project_File_18 = C:/elektronika/dct/mdct/source/MDCT.VHD
 
Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143931873 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 93
 
Project_File_19 = C:/elektronika/dct/mdct/source/DCT1D.vhd
 
Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145135163 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 93
 
Project_File_20 = C:/elektronika/dct/mdct/source/testbench/INPIMAGE.VHD
 
Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143979283 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 93
 
Project_File_21 = C:/elektronika/dct/mdct/source/MDCT_PKG.vhd
 
Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144447956 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 93
 
Project_File_22 = C:/elektronika/dct/MDCT/source/testbench/random1.vhd
 
Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder TESTBENCH last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 
Project_File_23 = C:/elektronika/dct/MDCT/source/xilinx/rome_xil.vhd
 
Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 
Project_Sim_Count = 0
 
Project_Folder_Count = 5
 
Project_Folder_0 = XILINX
 
Project_Folder_P_0 = folder SOURCE
 
Project_Folder_1 = TESTBENCH
 
Project_Folder_P_1 = folder SOURCE
 
Project_Folder_2 = SOURCE
 
Project_Folder_P_2 = folder {Top Level}
 
Project_Folder_3 = MODELSIM
 
Project_Folder_P_3 = folder {Top Level}
 
Project_Folder_4 = PAR
 
Project_Folder_P_4 = folder {Top Level}
 
Echo_Compile_Output = 0
 
Save_Compile_Report = 1
 
Project_Opt_Count = 0
 
ForceSoftPaths = 1
 
ReOpenSourceFiles = 1
 
VERILOG_DoubleClick = Edit
 
VERILOG_CustomDoubleClick =
 
VHDL_DoubleClick = Edit
 
VHDL_CustomDoubleClick =
 
PSL_DoubleClick = Edit
 
PSL_CustomDoubleClick =
 
TEXT_DoubleClick = Edit
 
TEXT_CustomDoubleClick =
 
SYSTEMC_DoubleClick = Edit
 
SYSTEMC_CustomDoubleClick =
 
TCL_DoubleClick = Edit
 
TCL_CustomDoubleClick =
 
MACRO_DoubleClick = Edit
 
MACRO_CustomDoubleClick =
 
VCD_DoubleClick = Edit
 
VCD_CustomDoubleClick =
 
SDF_DoubleClick = Edit
 
SDF_CustomDoubleClick =
 
XML_DoubleClick = Edit
 
XML_CustomDoubleClick =
 
LOGFILE_DoubleClick = Edit
 
LOGFILE_CustomDoubleClick =
 
EditorState = {tabbed horizontal 1} {C:/elektronika/dct/MDCT/source/DCT1D.vhd 0 0} {C:/elektronika/dct/MDCT/source/testbench/INPIMAGE.VHD 0 0} {F:/Xilinx/vhdl/src/simprims/simprim_VITAL_mti.vhd 0 0} {C:/elektronika/dct/MDCT/source/testbench/MDCTTB_PKG.vhd 0 1}
 
Project_Major_Version = 6
 
Project_Minor_Version = 1

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