| Line 53... |
Line 53... |
romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
reqwrfail : in STD_LOGIC;
|
|
|
|
ready : out STD_LOGIC; -- read from FIFO
|
|
odv : out STD_LOGIC;
|
odv : out STD_LOGIC;
|
dcto : out std_logic_vector(OP_W-1 downto 0);
|
dcto : out std_logic_vector(OP_W-1 downto 0);
|
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
| Line 79... |
Line 77... |
romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
|
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
|
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
ramwe : out STD_LOGIC;
|
ramwe : out STD_LOGIC;
|
requestwr : out STD_LOGIC;
|
wmemsel : out STD_LOGIC
|
releasewr : out STD_LOGIC
|
|
);
|
);
|
end DCT1D;
|
end DCT1D;
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- ARCHITECTURE
|
-- ARCHITECTURE
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
architecture RTL of DCT1D is
|
architecture RTL of DCT1D is
|
|
|
type STATE_T is
|
|
(
|
|
MEMREQ,
|
|
IDLE,
|
|
GET_ROM,
|
|
SUM,
|
|
WRITE_ODD
|
|
);
|
|
|
|
type ISTATE_T is
|
|
(
|
|
ACQUIRE_1ROW
|
|
);
|
|
|
|
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
|
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
|
|
|
signal ready_reg : STD_LOGIC;
|
|
signal databuf_reg : INPUT_DATA;
|
signal databuf_reg : INPUT_DATA;
|
signal latchbuf_reg : INPUT_DATA;
|
signal latchbuf_reg : INPUT_DATA;
|
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal inpcnt_reg : UNSIGNED(2 downto 0);
|
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal state_reg : STATE_T;
|
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal istate_reg : ISTATE_T;
|
|
signal cnt_reg : UNSIGNED(3 downto 0);
|
|
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
signal ramwe_s : STD_LOGIC;
|
signal ramwe_s : STD_LOGIC;
|
signal latch_done_reg : STD_LOGIC;
|
signal wmemsel_reg : STD_LOGIC;
|
signal latch_done_prev_reg : STD_LOGIC;
|
signal stage2_reg : STD_LOGIC;
|
signal requestwr_reg : STD_LOGIC;
|
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
|
signal releasewr_reg : STD_LOGIC;
|
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal col_tmp_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
|
begin
|
begin
|
|
|
ready_sg:
|
|
ready <= ready_reg;
|
|
|
|
ramwe_sg:
|
ramwe_sg:
|
ramwe <= ramwe_s;
|
ramwe <= ramwe_s;
|
|
|
ramdatai_sg:
|
ramdatai_sg:
|
ramdatai <= ramdatai_s;
|
ramdatai <= ramdatai_s;
|
| Line 138... |
Line 114... |
odv_sg:
|
odv_sg:
|
odv <= ramwe_s;
|
odv <= ramwe_s;
|
dcto_sg:
|
dcto_sg:
|
dcto <= ramdatai_s(RAMDATA_W-1) & ramdatai_s(RAMDATA_W-1) & ramdatai_s;
|
dcto <= ramdatai_s(RAMDATA_W-1) & ramdatai_s(RAMDATA_W-1) & ramdatai_s;
|
|
|
releasewr_sg:
|
wmemsel_sg:
|
releasewr <= releasewr_reg;
|
wmemsel <= wmemsel_reg;
|
requestwr_sg:
|
|
requestwr <= requestwr_reg;
|
process(clk,rst)
|
|
|
--------------------------------------
|
|
-- PROCESS
|
|
--------------------------------------
|
|
GET_PROC : process(rst,clk)
|
|
begin
|
begin
|
if rst = '1' then
|
if rst = '1' then
|
inpcnt_reg <= (others => '0');
|
inpcnt_reg <= (others => '0');
|
ready_reg <= '0';
|
|
latchbuf_reg <= (others => (others => '0'));
|
latchbuf_reg <= (others => (others => '0'));
|
latch_done_reg <= '0';
|
|
databuf_reg <= (others => (others => '0'));
|
databuf_reg <= (others => (others => '0'));
|
--latch_done_prev_reg <= '0';
|
stage2_reg <= '0';
|
|
stage2_cnt_reg <= (others => '1');
|
|
ramdatai_s <= (others => '0');
|
|
ramwe_s <= '0';
|
|
ramwaddro <= (others => '0');
|
|
col_reg <= (others => '0');
|
|
row_reg <= (others => '0');
|
|
wmemsel_reg <= '0';
|
|
col_2_reg <= (others => '0');
|
elsif clk = '1' and clk'event then
|
elsif clk = '1' and clk'event then
|
|
|
--latch_done_prev_reg <= latch_done_reg;
|
stage2_reg <= '0';
|
|
ramwe_s <= '0';
|
if latch_done_reg = '0' or
|
|
(state_reg=IDLE and reqwrfail='0' and latch_done_reg = '1') then
|
|
|
|
-- wait until DCT1D_PROC process 1D DCT computation
|
|
-- before latching new 8 input words
|
|
if (state_reg = IDLE and reqwrfail = '0' and latch_done_reg = '1') then
|
|
latch_done_reg <= '0';
|
|
end if;
|
|
|
|
|
--------------------------------
|
|
-- 1st stage
|
|
--------------------------------
|
if idv = '1' then
|
if idv = '1' then
|
-- read next data from input FIFO
|
|
ready_reg <= '1';
|
|
|
|
if ready_reg = '1' then
|
inpcnt_reg <= inpcnt_reg + 1;
|
|
|
-- right shift input data
|
-- right shift input data
|
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
|
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
|
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
|
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
|
|
|
inpcnt_reg <= inpcnt_reg + 1;
|
|
|
|
if inpcnt_reg = N-1 then
|
if inpcnt_reg = N-1 then
|
latch_done_reg <= '1';
|
|
ready_reg <= '0';
|
|
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
|
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
|
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
|
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
|
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
|
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
|
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
|
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
|
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
|
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
|
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
|
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
|
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
|
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
|
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
|
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
|
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
|
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
|
|
stage2_reg <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
else
|
--------------------------------
|
ready_reg <= '0';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
--------------------------------------
|
|
-- PROCESS
|
|
--------------------------------------
|
|
DCT1D_PROC: process(rst, clk)
|
|
begin
|
|
if rst = '1' then
|
|
col_reg <= (others => '0');
|
|
row_reg <= (others => '0');
|
|
state_reg <= MEMREQ;
|
|
cnt_reg <= (others => '0');
|
|
|
|
ramwaddro <= (others => '0');
|
|
ramdatai_s <= (others => '0');
|
|
ramwe_s <= '0';
|
|
releasewr_reg <= '0';
|
|
col_tmp_reg <= (others => '0');
|
|
requestwr_reg <= '0';
|
|
elsif rising_edge(clk) then
|
|
|
|
case state_reg is
|
|
|
|
when MEMREQ =>
|
|
|
|
ramwe_s <= '0';
|
|
|
|
-- release memory fully written
|
|
releasewr_reg <= '0';
|
|
|
|
-- request free memory for writing
|
|
requestwr_reg <= '1';
|
|
|
|
-- DBUFCTL 1T delay
|
|
if requestwr_reg = '1' then
|
|
requestwr_reg <= '0';
|
|
state_reg <= IDLE;
|
|
end if;
|
|
|
|
----------------------
|
|
-- wait for input data
|
|
----------------------
|
|
when IDLE =>
|
|
|
|
ramwe_s <= '0';
|
|
|
|
-- failure to allocate any memory buffer
|
|
if reqwrfail = '1' then
|
|
-- restart allocation procedure
|
|
state_reg <= MEMREQ;
|
|
-- wait until 8 input words are latched in latchbuf_reg
|
|
-- by GET_PROC
|
|
elsif latch_done_reg = '1' then
|
|
state_reg <= SUM;
|
|
end if;
|
|
|
|
----------------------
|
|
-- get MAC results from ROM even and ROM odd memories
|
|
----------------------
|
|
when GET_ROM =>
|
|
|
|
ramwe_s <='0';
|
|
|
|
state_reg <= SUM;
|
|
|
|
---------------------
|
--------------------------------
|
-- do distributed arithmetic sum on even part,
|
-- 2nd stage
|
-- write even part to RAM
|
--------------------------------
|
---------------------
|
if stage2_cnt_reg < N then
|
when SUM =>
|
|
|
|
|
if stage2_cnt_reg(0) = '0' then
|
ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
|
ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
|
(RESIZE(SIGNED(romedatao0),DA_W) +
|
(RESIZE(SIGNED(romedatao0),DA_W) +
|
(RESIZE(SIGNED(romedatao1),DA_W-1) & '0') +
|
(RESIZE(SIGNED(romedatao1),DA_W-1) & '0') +
|
(RESIZE(SIGNED(romedatao2),DA_W-2) & "00") +
|
(RESIZE(SIGNED(romedatao2),DA_W-2) & "00") +
|
(RESIZE(SIGNED(romedatao3),DA_W-3) & "000") +
|
(RESIZE(SIGNED(romedatao3),DA_W-3) & "000") +
|
| Line 280... |
Line 180... |
(RESIZE(SIGNED(romedatao5),DA_W-5) & "00000") +
|
(RESIZE(SIGNED(romedatao5),DA_W-5) & "00000") +
|
(RESIZE(SIGNED(romedatao6),DA_W-6) & "000000") +
|
(RESIZE(SIGNED(romedatao6),DA_W-6) & "000000") +
|
(RESIZE(SIGNED(romedatao7),DA_W-7) & "0000000") -
|
(RESIZE(SIGNED(romedatao7),DA_W-7) & "0000000") -
|
(RESIZE(SIGNED(romedatao8),DA_W-8) & "00000000"),
|
(RESIZE(SIGNED(romedatao8),DA_W-8) & "00000000"),
|
DA_W)(DA_W-1 downto 12));
|
DA_W)(DA_W-1 downto 12));
|
|
else
|
-- write even part
|
|
ramwe_s <= '1';
|
|
-- reverse col/row order for transposition purpose
|
|
ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg);
|
|
|
|
col_reg <= col_reg + 1;
|
|
col_tmp_reg <= col_reg + 2;
|
|
|
|
|
|
state_reg <= WRITE_ODD;
|
|
|
|
---------------------
|
|
-- do distributed arithmetic sum on odd part,
|
|
-- write odd part to RAM
|
|
---------------------
|
|
when WRITE_ODD =>
|
|
|
|
-- write odd part
|
|
--ramwe_s <= '1';
|
|
|
|
ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
|
ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
|
(RESIZE(SIGNED(romodatao0),DA_W) +
|
(RESIZE(SIGNED(romodatao0),DA_W) +
|
(RESIZE(SIGNED(romodatao1),DA_W-1) & '0') +
|
(RESIZE(SIGNED(romodatao1),DA_W-1) & '0') +
|
(RESIZE(SIGNED(romodatao2),DA_W-2) & "00") +
|
(RESIZE(SIGNED(romodatao2),DA_W-2) & "00") +
|
(RESIZE(SIGNED(romodatao3),DA_W-3) & "000") +
|
(RESIZE(SIGNED(romodatao3),DA_W-3) & "000") +
|
| Line 312... |
Line 192... |
(RESIZE(SIGNED(romodatao5),DA_W-5) & "00000") +
|
(RESIZE(SIGNED(romodatao5),DA_W-5) & "00000") +
|
(RESIZE(SIGNED(romodatao6),DA_W-6) & "000000") +
|
(RESIZE(SIGNED(romodatao6),DA_W-6) & "000000") +
|
(RESIZE(SIGNED(romodatao7),DA_W-7) & "0000000") -
|
(RESIZE(SIGNED(romodatao7),DA_W-7) & "0000000") -
|
(RESIZE(SIGNED(romodatao8),DA_W-8) & "00000000"),
|
(RESIZE(SIGNED(romodatao8),DA_W-8) & "00000000"),
|
DA_W)(DA_W-1 downto 12));
|
DA_W)(DA_W-1 downto 12));
|
|
end if;
|
|
|
-- write odd part
|
stage2_cnt_reg <= stage2_cnt_reg + 1;
|
-- reverse col/row order for transposition purpose
|
|
ramwaddro <= STD_LOGIC_VECTOR(col_reg & row_reg);
|
|
|
|
-- move to next column
|
-- write RAM
|
|
ramwe_s <= '1';
|
|
-- reverse col/row order for transposition purpose
|
|
ramwaddro <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
|
|
-- increment column counter
|
col_reg <= col_reg + 1;
|
col_reg <= col_reg + 1;
|
col_tmp_reg <= col_reg + 1;
|
col_2_reg <= col_2_reg + 1;
|
|
|
-- finished processing one input row
|
-- finished processing one input row
|
if col_reg = N - 1 then
|
if col_reg = 0 then
|
row_reg <= row_reg + 1;
|
row_reg <= row_reg + 1;
|
col_reg <= (others => '0');
|
-- switch to 2nd memory
|
col_tmp_reg <= (others => '0');
|
|
if row_reg = N - 1 then
|
if row_reg = N - 1 then
|
releasewr_reg <= '1';
|
wmemsel_reg <= not wmemsel_reg;
|
state_reg <= MEMREQ;
|
col_reg <= (others => '0');
|
else
|
|
state_reg <= IDLE;
|
|
end if;
|
end if;
|
else
|
|
state_reg <= SUM;
|
|
end if;
|
end if;
|
--------------------------------
|
|
-- OTHERS
|
end if;
|
--------------------------------
|
|
when others =>
|
if stage2_reg = '1' then
|
state_reg <= IDLE;
|
stage2_cnt_reg <= (others => '0');
|
end case;
|
col_reg <= (0=>'1',others => '0');
|
|
col_2_reg <= (others => '0');
|
|
end if;
|
|
----------------------------------
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- read precomputed MAC results from LUT
|
-- read precomputed MAC results from LUT
|
romeaddro0 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(0)(0) &
|
databuf_reg(0)(0) &
|
databuf_reg(1)(0) &
|
databuf_reg(1)(0) &
|
databuf_reg(2)(0) &
|
databuf_reg(2)(0) &
|
databuf_reg(3)(0);
|
databuf_reg(3)(0);
|
romeaddro1 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(0)(1) &
|
databuf_reg(0)(1) &
|
databuf_reg(1)(1) &
|
databuf_reg(1)(1) &
|
databuf_reg(2)(1) &
|
databuf_reg(2)(1) &
|
databuf_reg(3)(1);
|
databuf_reg(3)(1);
|
romeaddro2 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(0)(2) &
|
databuf_reg(0)(2) &
|
databuf_reg(1)(2) &
|
databuf_reg(1)(2) &
|
databuf_reg(2)(2) &
|
databuf_reg(2)(2) &
|
databuf_reg(3)(2);
|
databuf_reg(3)(2);
|
romeaddro3 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(0)(3) &
|
databuf_reg(0)(3) &
|
databuf_reg(1)(3) &
|
databuf_reg(1)(3) &
|
databuf_reg(2)(3) &
|
databuf_reg(2)(3) &
|
databuf_reg(3)(3);
|
databuf_reg(3)(3);
|
romeaddro4 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
romeaddro4 <= STD_LOGIC_VECTOR( col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(0)(4) &
|
databuf_reg(0)(4) &
|
databuf_reg(1)(4) &
|
databuf_reg(1)(4) &
|
databuf_reg(2)(4) &
|
databuf_reg(2)(4) &
|
databuf_reg(3)(4);
|
databuf_reg(3)(4);
|
romeaddro5 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
romeaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(0)(5) &
|
databuf_reg(0)(5) &
|
databuf_reg(1)(5) &
|
databuf_reg(1)(5) &
|
databuf_reg(2)(5) &
|
databuf_reg(2)(5) &
|
databuf_reg(3)(5);
|
databuf_reg(3)(5);
|
romeaddro6 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
romeaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(0)(6) &
|
databuf_reg(0)(6) &
|
databuf_reg(1)(6) &
|
databuf_reg(1)(6) &
|
databuf_reg(2)(6) &
|
databuf_reg(2)(6) &
|
databuf_reg(3)(6);
|
databuf_reg(3)(6);
|
romeaddro7 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
romeaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(0)(7) &
|
databuf_reg(0)(7) &
|
databuf_reg(1)(7) &
|
databuf_reg(1)(7) &
|
databuf_reg(2)(7) &
|
databuf_reg(2)(7) &
|
databuf_reg(3)(7);
|
databuf_reg(3)(7);
|
romeaddro8 <= STD_LOGIC_VECTOR(col_tmp_reg(RAMADRR_W/2-1 downto 1)) &
|
romeaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(0)(8) &
|
databuf_reg(0)(8) &
|
databuf_reg(1)(8) &
|
databuf_reg(1)(8) &
|
databuf_reg(2)(8) &
|
databuf_reg(2)(8) &
|
databuf_reg(3)(8);
|
databuf_reg(3)(8);
|
|
|
|
|
-- odd
|
-- odd
|
romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(4)(0) &
|
databuf_reg(4)(0) &
|
databuf_reg(5)(0) &
|
databuf_reg(5)(0) &
|
databuf_reg(6)(0) &
|
databuf_reg(6)(0) &
|
| Line 439... |
Line 319... |
databuf_reg(4)(8) &
|
databuf_reg(4)(8) &
|
databuf_reg(5)(8) &
|
databuf_reg(5)(8) &
|
databuf_reg(6)(8) &
|
databuf_reg(6)(8) &
|
databuf_reg(7)(8);
|
databuf_reg(7)(8);
|
|
|
|
|
end RTL;
|
end RTL;
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
No newline at end of file
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No newline at end of file
|
