| Line 30... |
Line 30... |
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entity DCT2D is
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entity DCT2D is
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port(
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port(
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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rst : in std_logic;
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rst : in std_logic;
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romedatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao : in T_ROM2DATAO;
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romedatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao : in T_ROM2DATAO;
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romedatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romedatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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romodatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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dataready : in STD_LOGIC;
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dataready : in STD_LOGIC;
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odv : out STD_LOGIC;
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odv : out STD_LOGIC;
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dcto : out std_logic_vector(OP_W-1 downto 0);
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dcto : out std_logic_vector(OP_W-1 downto 0);
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romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro : out T_ROM2ADDRO;
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romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro : out T_ROM2ADDRO;
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romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romeaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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romoaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
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rmemsel : out STD_LOGIC;
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rmemsel : out STD_LOGIC;
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datareadyack : out STD_LOGIC
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datareadyack : out STD_LOGIC
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);
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);
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| Line 103... |
Line 63... |
signal rmemsel_reg : STD_LOGIC;
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signal rmemsel_reg : STD_LOGIC;
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signal stage1_reg : STD_LOGIC;
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signal stage1_reg : STD_LOGIC;
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signal stage2_reg : STD_LOGIC;
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signal stage2_reg : STD_LOGIC;
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signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
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signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
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signal dataready_2_reg : STD_LOGIC;
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signal dataready_2_reg : STD_LOGIC;
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signal even_not_odd : std_logic;
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signal even_not_odd_d1 : std_logic;
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signal even_not_odd_d2 : std_logic;
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signal even_not_odd_d3 : std_logic;
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signal even_not_odd_d4 : std_logic;
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signal odv_d0 : std_logic;
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signal odv_d1 : std_logic;
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signal odv_d2 : std_logic;
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signal odv_d3 : std_logic;
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signal odv_d4 : std_logic;
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signal odv_d5 : std_logic;
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signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);
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signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);
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signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);
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signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);
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signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);
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signal romedatao_d1 : T_ROM2DATAO;
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signal romodatao_d1 : T_ROM2DATAO;
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signal romedatao_d2 : T_ROM2DATAO;
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signal romodatao_d2 : T_ROM2DATAO;
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signal romedatao_d3 : T_ROM2DATAO;
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signal romodatao_d3 : T_ROM2DATAO;
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signal romedatao_d4 : T_ROM2DATAO;
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signal romodatao_d4 : T_ROM2DATAO;
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begin
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begin
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ramraddro_sg:
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ramraddro_sg:
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ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
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ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
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rmemsel_sg:
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rmemsel_sg:
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rmemsel <= rmemsel_reg;
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rmemsel <= rmemsel_reg;
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process(clk)
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process(clk,rst)
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begin
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begin
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if clk='1' and clk'event then
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if rst = '1' then
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if rst = '1' then
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stage2_cnt_reg <= (others => '1');
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stage2_cnt_reg <= (others => '1');
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rmemsel_reg <= '0';
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rmemsel_reg <= '0';
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stage1_reg <= '0';
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stage1_reg <= '0';
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stage2_reg <= '0';
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stage2_reg <= '0';
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| Line 126... |
Line 108... |
rowram_reg <= (others => '0');
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rowram_reg <= (others => '0');
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col_reg <= (others => '0');
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col_reg <= (others => '0');
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row_reg <= (others => '0');
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row_reg <= (others => '0');
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latchbuf_reg <= (others => (others => '0'));
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latchbuf_reg <= (others => (others => '0'));
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databuf_reg <= (others => (others => '0'));
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databuf_reg <= (others => (others => '0'));
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dcto <= (others => '0');
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odv_d0 <= '0';
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odv <= '0';
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colr_reg <= (others => '0');
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colr_reg <= (others => '0');
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rowr_reg <= (others => '0');
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rowr_reg <= (others => '0');
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dataready_2_reg <= '0';
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dataready_2_reg <= '0';
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else
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elsif clk='1' and clk'event then
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stage2_reg <= '0';
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stage2_reg <= '0';
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odv <= '0';
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odv_d0 <= '0';
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datareadyack <= '0';
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datareadyack <= '0';
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dataready_2_reg <= dataready;
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dataready_2_reg <= dataready;
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----------------------------------
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----------------------------------
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-- read DCT 1D to barrel shifer
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-- read DCT 1D to barrel shifer
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----------------------------------
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----------------------------------
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| Line 183... |
Line 162... |
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--------------------------------
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--------------------------------
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-- 2nd stage
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-- 2nd stage
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--------------------------------
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--------------------------------
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if stage2_cnt_reg < N then
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if stage2_cnt_reg < N then
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if stage2_cnt_reg(0) = '0' then
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dcto <= STD_LOGIC_VECTOR(RESIZE
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(RESIZE(SIGNED(romedatao0),DA2_W) +
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(RESIZE(SIGNED(romedatao1),DA2_W-1) & '0') +
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(RESIZE(SIGNED(romedatao2),DA2_W-2) & "00") +
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(RESIZE(SIGNED(romedatao3),DA2_W-3) & "000") +
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(RESIZE(SIGNED(romedatao4),DA2_W-4) & "0000") +
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(RESIZE(SIGNED(romedatao5),DA2_W-5) & "00000") +
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(RESIZE(SIGNED(romedatao6),DA2_W-6) & "000000") +
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(RESIZE(SIGNED(romedatao7),DA2_W-7) & "0000000") +
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(RESIZE(SIGNED(romedatao8),DA2_W-8) & "00000000") +
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(RESIZE(SIGNED(romedatao9),DA2_W-9) & "000000000") -
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(RESIZE(SIGNED(romedatao10),DA2_W-10) & "0000000000"),
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DA2_W)(DA2_W-1 downto 12));
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else
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dcto <= STD_LOGIC_VECTOR(RESIZE
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(RESIZE(SIGNED(romodatao0),DA2_W) +
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(RESIZE(SIGNED(romodatao1),DA2_W-1) & '0') +
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(RESIZE(SIGNED(romodatao2),DA2_W-2) & "00") +
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(RESIZE(SIGNED(romodatao3),DA2_W-3) & "000") +
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(RESIZE(SIGNED(romodatao4),DA2_W-4) & "0000") +
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(RESIZE(SIGNED(romodatao5),DA2_W-5) & "00000") +
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(RESIZE(SIGNED(romodatao6),DA2_W-6) & "000000") +
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(RESIZE(SIGNED(romodatao7),DA2_W-7) & "0000000") +
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(RESIZE(SIGNED(romodatao8),DA2_W-8) & "00000000") +
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(RESIZE(SIGNED(romodatao9),DA2_W-9) & "000000000") -
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(RESIZE(SIGNED(romodatao10),DA2_W-10) & "0000000000"),
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DA2_W)(DA2_W-1 downto 12));
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end if;
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stage2_cnt_reg <= stage2_cnt_reg + 1;
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stage2_cnt_reg <= stage2_cnt_reg + 1;
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-- write RAM
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-- output data valid
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odv <= '1';
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odv_d0 <= '1';
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-- increment column counter
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-- increment column counter
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col_reg <= col_reg + 1;
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col_reg <= col_reg + 1;
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-- finished processing one input row
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-- finished processing one input row
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| Line 247... |
Line 195... |
colr_reg <= (0=>'1',others => '0');
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colr_reg <= (0=>'1',others => '0');
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datareadyack <= '1';
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datareadyack <= '1';
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end if;
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end if;
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----------------------------------
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----------------------------------
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end if;
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end process;
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p_data_pipe : process(CLK, RST)
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begin
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if RST = '1' then
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even_not_odd <= '0';
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even_not_odd_d1 <= '0';
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even_not_odd_d2 <= '0';
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even_not_odd_d3 <= '0';
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even_not_odd_d4 <= '0';
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odv_d1 <= '0';
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odv_d2 <= '0';
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odv_d3 <= '0';
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odv_d4 <= '0';
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odv_d5 <= '0';
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dcto_1 <= (others => '0');
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dcto_2 <= (others => '0');
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dcto_3 <= (others => '0');
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dcto_4 <= (others => '0');
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dcto_5 <= (others => '0');
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elsif CLK'event and CLK = '1' then
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even_not_odd <= stage2_cnt_reg(0);
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even_not_odd_d1 <= even_not_odd;
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even_not_odd_d2 <= even_not_odd_d1;
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even_not_odd_d3 <= even_not_odd_d2;
|
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even_not_odd_d4 <= even_not_odd_d3;
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odv_d1 <= odv_d0;
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odv_d2 <= odv_d1;
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odv_d3 <= odv_d2;
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odv_d4 <= odv_d3;
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odv_d5 <= odv_d4;
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|
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if even_not_odd = '0' then
|
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dcto_1 <= STD_LOGIC_VECTOR(RESIZE
|
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(RESIZE(SIGNED(romedatao(0)),DA2_W) +
|
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(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
|
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(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
|
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DA2_W));
|
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else
|
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dcto_1 <= STD_LOGIC_VECTOR(RESIZE
|
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(RESIZE(SIGNED(romodatao(0)),DA2_W) +
|
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(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
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(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
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DA2_W));
|
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end if;
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|
|
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if even_not_odd_d1 = '0' then
|
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dcto_2 <= STD_LOGIC_VECTOR(RESIZE
|
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(signed(dcto_1) +
|
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(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
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(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
|
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DA2_W));
|
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else
|
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dcto_2 <= STD_LOGIC_VECTOR(RESIZE
|
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(signed(dcto_1) +
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(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
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(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
|
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DA2_W));
|
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end if;
|
|
|
|
if even_not_odd_d2 = '0' then
|
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dcto_3 <= STD_LOGIC_VECTOR(RESIZE
|
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(signed(dcto_2) +
|
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(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
|
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(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
|
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DA2_W));
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else
|
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dcto_3 <= STD_LOGIC_VECTOR(RESIZE
|
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(signed(dcto_2) +
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(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
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(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
|
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DA2_W));
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end if;
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|
|
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if even_not_odd_d3 = '0' then
|
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dcto_4 <= STD_LOGIC_VECTOR(RESIZE
|
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(signed(dcto_3) +
|
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(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
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(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
|
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DA2_W));
|
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else
|
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dcto_4 <= STD_LOGIC_VECTOR(RESIZE
|
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(signed(dcto_3) +
|
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(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
|
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(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
|
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DA2_W));
|
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end if;
|
|
|
|
if even_not_odd_d4 = '0' then
|
|
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
|
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(signed(dcto_4) +
|
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(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
|
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(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
|
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DA2_W));
|
|
else
|
|
dcto_5 <= STD_LOGIC_VECTOR(RESIZE
|
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(signed(dcto_4) +
|
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(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
|
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(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
|
|
DA2_W));
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
dcto <= dcto_5(DA2_W-1 downto 12);
|
|
odv <= odv_d5;
|
|
|
|
p_romaddr : process(CLK, RST)
|
|
begin
|
|
if RST = '1' then
|
|
romeaddro <= (others => (others => '0'));
|
|
romoaddro <= (others => (others => '0'));
|
|
elsif CLK'event and CLK = '1' then
|
|
for i in 0 to 10 loop
|
-- read precomputed MAC results from LUT
|
-- read precomputed MAC results from LUT
|
romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(0)(0) &
|
databuf_reg(0)(i) &
|
databuf_reg(1)(0) &
|
databuf_reg(1)(i) &
|
databuf_reg(2)(0) &
|
databuf_reg(2)(i) &
|
databuf_reg(3)(0);
|
databuf_reg(3)(i);
|
romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
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databuf_reg(0)(1) &
|
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databuf_reg(1)(1) &
|
|
databuf_reg(2)(1) &
|
|
databuf_reg(3)(1);
|
|
romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(2) &
|
|
databuf_reg(1)(2) &
|
|
databuf_reg(2)(2) &
|
|
databuf_reg(3)(2);
|
|
romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(3) &
|
|
databuf_reg(1)(3) &
|
|
databuf_reg(2)(3) &
|
|
databuf_reg(3)(3);
|
|
romeaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(4) &
|
|
databuf_reg(1)(4) &
|
|
databuf_reg(2)(4) &
|
|
databuf_reg(3)(4);
|
|
romeaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(5) &
|
|
databuf_reg(1)(5) &
|
|
databuf_reg(2)(5) &
|
|
databuf_reg(3)(5);
|
|
romeaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(6) &
|
|
databuf_reg(1)(6) &
|
|
databuf_reg(2)(6) &
|
|
databuf_reg(3)(6);
|
|
romeaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(7) &
|
|
databuf_reg(1)(7) &
|
|
databuf_reg(2)(7) &
|
|
databuf_reg(3)(7);
|
|
romeaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(8) &
|
|
databuf_reg(1)(8) &
|
|
databuf_reg(2)(8) &
|
|
databuf_reg(3)(8);
|
|
romeaddro9 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(9) &
|
|
databuf_reg(1)(9) &
|
|
databuf_reg(2)(9) &
|
|
databuf_reg(3)(9);
|
|
romeaddro10 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(10) &
|
|
databuf_reg(1)(10) &
|
|
databuf_reg(2)(10) &
|
|
databuf_reg(3)(10);
|
|
-- odd
|
-- odd
|
romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(4)(0) &
|
databuf_reg(4)(i) &
|
databuf_reg(5)(0) &
|
databuf_reg(5)(i) &
|
databuf_reg(6)(0) &
|
databuf_reg(6)(i) &
|
databuf_reg(7)(0);
|
databuf_reg(7)(i);
|
romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
end loop;
|
databuf_reg(4)(1) &
|
end if;
|
databuf_reg(5)(1) &
|
end process;
|
databuf_reg(6)(1) &
|
|
databuf_reg(7)(1);
|
p_romdatao_dly : process(CLK, RST)
|
romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
begin
|
databuf_reg(4)(2) &
|
if RST = '1' then
|
databuf_reg(5)(2) &
|
romedatao_d1 <= (others => (others => '0'));
|
databuf_reg(6)(2) &
|
romodatao_d1 <= (others => (others => '0'));
|
databuf_reg(7)(2);
|
romedatao_d2 <= (others => (others => '0'));
|
romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
romodatao_d2 <= (others => (others => '0'));
|
databuf_reg(4)(3) &
|
romedatao_d3 <= (others => (others => '0'));
|
databuf_reg(5)(3) &
|
romodatao_d3 <= (others => (others => '0'));
|
databuf_reg(6)(3) &
|
romedatao_d4 <= (others => (others => '0'));
|
databuf_reg(7)(3);
|
romodatao_d4 <= (others => (others => '0'));
|
romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
elsif CLK'event and CLK = '1' then
|
databuf_reg(4)(4) &
|
romedatao_d1 <= romedatao;
|
databuf_reg(5)(4) &
|
romodatao_d1 <= romodatao;
|
databuf_reg(6)(4) &
|
romedatao_d2 <= romedatao_d1;
|
databuf_reg(7)(4);
|
romodatao_d2 <= romodatao_d1;
|
romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
romedatao_d3 <= romedatao_d2;
|
databuf_reg(4)(5) &
|
romodatao_d3 <= romodatao_d2;
|
databuf_reg(5)(5) &
|
romedatao_d4 <= romedatao_d3;
|
databuf_reg(6)(5) &
|
romodatao_d4 <= romodatao_d3;
|
databuf_reg(7)(5);
|
end if;
|
romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
end process;
|
databuf_reg(4)(6) &
|
|
databuf_reg(5)(6) &
|
|
databuf_reg(6)(6) &
|
|
databuf_reg(7)(6);
|
|
romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(4)(7) &
|
|
databuf_reg(5)(7) &
|
|
databuf_reg(6)(7) &
|
|
databuf_reg(7)(7);
|
|
romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(4)(8) &
|
|
databuf_reg(5)(8) &
|
|
databuf_reg(6)(8) &
|
|
databuf_reg(7)(8);
|
|
romoaddro9 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(4)(9) &
|
|
databuf_reg(5)(9) &
|
|
databuf_reg(6)(9) &
|
|
databuf_reg(7)(9);
|
|
romoaddro10 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(4)(10) &
|
|
databuf_reg(5)(10) &
|
|
databuf_reg(6)(10) &
|
|
databuf_reg(7)(10);
|
|
|
|
end RTL;
|
end RTL;
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
