| Line 142... |
Line 142... |
istate_reg <= IDLE_I;
|
istate_reg <= IDLE_I;
|
latch_done_reg <= '0';
|
latch_done_reg <= '0';
|
completed_reg <= '0';
|
completed_reg <= '0';
|
requestrd_reg <= '0';
|
requestrd_reg <= '0';
|
releaserd_reg <= '0';
|
releaserd_reg <= '0';
|
|
databuf_reg <= (others => (others => '0'));
|
elsif clk = '1' and clk'event then
|
elsif clk = '1' and clk'event then
|
case istate_reg is
|
case istate_reg is
|
|
|
----------------------
|
----------------------
|
-- IDLE
|
-- IDLE
|
----------------------
|
----------------------
|
when IDLE_I =>
|
when IDLE_I =>
|
-- one of ram buffers has new data
|
-- one of ram buffers has new data, process it
|
if dataready = '1' then
|
if dataready = '1' then
|
requestrd_reg <= '1';
|
requestrd_reg <= '1';
|
end if;
|
end if;
|
-- give 1T delay needed by DBUFCTL
|
-- give 1T delay needed by DBUFCTL
|
if requestrd_reg = '1' then
|
if requestrd_reg = '1' then
|
requestrd_reg <= '0';
|
requestrd_reg <= '0';
|
istate_reg <= ACQUIRE_1ROW;
|
istate_reg <= ACQUIRE_1ROW;
|
|
-- to account for 1T RAM delay, increment RAM address counter
|
|
colram_reg <= (0=>'1',others => '0');
|
end if;
|
end if;
|
|
|
----------------------
|
----------------------
|
-- latch input data to barrel shifter
|
-- latch input data to barrel shifter
|
----------------------
|
----------------------
|
| Line 186... |
Line 189... |
end if;
|
end if;
|
colram_reg <= (others => '0');
|
colram_reg <= (others => '0');
|
rowram_reg <= rowram_reg + 1;
|
rowram_reg <= rowram_reg + 1;
|
-- 8 point input latched
|
-- 8 point input latched
|
latch_done_reg <= '1';
|
latch_done_reg <= '1';
|
--istate_reg <= WAITF;
|
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
|
|
databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
|
|
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
|
|
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
|
|
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
|
|
databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
|
|
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
|
|
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
|
|
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
|
end if;
|
end if;
|
|
|
-- failure to allocate memory buffer
|
-- failure to allocate memory buffer
|
-- should never happen?
|
-- should never happen?
|
if reqrdfail = '1' then
|
if reqrdfail = '1' then
|
| Line 202... |
Line 213... |
-- before latching new 8 input words
|
-- before latching new 8 input words
|
if state_reg = IDLE then
|
if state_reg = IDLE then
|
latch_done_reg <= '0';
|
latch_done_reg <= '0';
|
if completed_reg = '1' then
|
if completed_reg = '1' then
|
completed_reg <= '0';
|
completed_reg <= '0';
|
|
colram_reg <= (others => '0');
|
istate_reg <= IDLE_I;
|
istate_reg <= IDLE_I;
|
else
|
else
|
istate_reg <= ACQUIRE_1ROW;
|
istate_reg <= ACQUIRE_1ROW;
|
|
-- to account for 1T RAM delay, increment RAM address counter
|
|
colram_reg <= (0=>'1',others => '0');
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
| Line 223... |
Line 237... |
if rst = '1' then
|
if rst = '1' then
|
col_reg <= (others => '0');
|
col_reg <= (others => '0');
|
row_reg <= (others => '0');
|
row_reg <= (others => '0');
|
state_reg <= IDLE;
|
state_reg <= IDLE;
|
cnt_reg <= (others => '0');
|
cnt_reg <= (others => '0');
|
databuf_reg <= (others => (others => '0'));
|
|
odv <= '0';
|
odv <= '0';
|
dcto <= (others => '0');
|
dcto <= (others => '0');
|
col_tmp_reg <= (others => '0');
|
col_tmp_reg <= (others => '0');
|
elsif rising_edge(clk) then
|
elsif rising_edge(clk) then
|
|
|
| Line 240... |
Line 253... |
|
|
odv <= '0';
|
odv <= '0';
|
-- wait until 8 input words are latched in latchbuf_reg
|
-- wait until 8 input words are latched in latchbuf_reg
|
-- by GET_PROC
|
-- by GET_PROC
|
if latch_done_reg = '1' then
|
if latch_done_reg = '1' then
|
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
|
|
databuf_reg(0) <= latchbuf_reg(0)+latchbuf_reg(7);
|
state_reg <= SUM;
|
databuf_reg(1) <= latchbuf_reg(1)+latchbuf_reg(6);
|
|
databuf_reg(2) <= latchbuf_reg(2)+latchbuf_reg(5);
|
|
databuf_reg(3) <= latchbuf_reg(3)+latchbuf_reg(4);
|
|
databuf_reg(4) <= latchbuf_reg(0)-latchbuf_reg(7);
|
|
databuf_reg(5) <= latchbuf_reg(1)-latchbuf_reg(6);
|
|
databuf_reg(6) <= latchbuf_reg(2)-latchbuf_reg(5);
|
|
databuf_reg(7) <= latchbuf_reg(3)-latchbuf_reg(4);
|
|
state_reg <= GET_ROM;
|
|
end if;
|
end if;
|
|
|
----------------------
|
----------------------
|
-- get MAC results from ROM even and ROM odd memories
|
-- get MAC results from ROM even and ROM odd memories
|
----------------------
|
----------------------
|
