| Line 34... |
Line 34... |
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
rst : in std_logic;
|
rst : in std_logic;
|
dcti : in std_logic_vector(IP_W-1 downto 0);
|
dcti : in std_logic_vector(IP_W-1 downto 0);
|
idv : in STD_LOGIC;
|
idv : in STD_LOGIC;
|
|
|
ready : out STD_LOGIC; -- ready for input data
|
fiforead : out STD_LOGIC; -- ready for input data
|
odv : out STD_LOGIC;
|
odv : out STD_LOGIC;
|
dcto : out std_logic_vector(COE_W-1 downto 0);
|
dcto : out std_logic_vector(COE_W-1 downto 0);
|
-- debug
|
-- debug
|
odv1 : out STD_LOGIC;
|
odv1 : out STD_LOGIC;
|
dcto1 : out std_logic_vector(OP_W-1 downto 0)
|
dcto1 : out std_logic_vector(OP_W-1 downto 0)
|
| Line 73... |
Line 73... |
romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
reqwrfail : in STD_LOGIC;
|
|
|
|
ready : out STD_LOGIC; -- read from FIFO
|
|
odv : out STD_LOGIC;
|
odv : out STD_LOGIC;
|
dcto : out std_logic_vector(OP_W-1 downto 0);
|
dcto : out std_logic_vector(OP_W-1 downto 0);
|
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
| Line 99... |
Line 97... |
romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
|
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
|
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
ramwe : out STD_LOGIC;
|
ramwe : out STD_LOGIC;
|
requestwr : out STD_LOGIC;
|
wmemsel : out STD_LOGIC
|
releasewr : out STD_LOGIC
|
|
);
|
);
|
end component;
|
end component;
|
|
|
------------------------------
|
------------------------------
|
-- 1D DCT (2nd stage)
|
-- 1D DCT (2nd stage)
|
| Line 134... |
Line 131... |
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
reqrdfail : in STD_LOGIC;
|
|
dataready : in STD_LOGIC;
|
dataready : in STD_LOGIC;
|
|
|
odv : out STD_LOGIC;
|
odv : out STD_LOGIC;
|
dcto : out std_logic_vector(OP_W-1 downto 0);
|
dcto : out std_logic_vector(OP_W-1 downto 0);
|
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
| Line 162... |
Line 158... |
romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romoaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romoaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romoaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romoaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
|
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
|
requestrd : out STD_LOGIC;
|
rmemsel : out STD_LOGIC;
|
releaserd : out STD_LOGIC
|
datareadyack : out STD_LOGIC
|
);
|
);
|
end component;
|
end component;
|
|
|
------------------------------
|
------------------------------
|
-- RAM
|
-- RAM
|
| Line 213... |
Line 209... |
------------------------------
|
------------------------------
|
component DBUFCTL is
|
component DBUFCTL is
|
port(
|
port(
|
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
rst : in STD_LOGIC;
|
rst : in STD_LOGIC;
|
requestwr : in STD_LOGIC;
|
wmemsel : in STD_LOGIC;
|
requestrd : in STD_LOGIC;
|
rmemsel : in STD_LOGIC;
|
releasewr : in STD_LOGIC;
|
datareadyack : in STD_LOGIC;
|
releaserd : in STD_LOGIC;
|
|
|
|
memswitchwr : out STD_LOGIC;
|
memswitchwr : out STD_LOGIC;
|
memswitchrd : out STD_LOGIC;
|
memswitchrd : out STD_LOGIC;
|
reqwrfail : out STD_LOGIC;
|
|
reqrdfail : out STD_LOGIC;
|
|
dataready : out STD_LOGIC
|
dataready : out STD_LOGIC
|
);
|
);
|
end component;
|
end component;
|
|
|
signal romedatao0_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
signal romedatao0_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
| Line 322... |
Line 315... |
signal ramdatao2_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
signal ramdatao2_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
signal ramwe1_s : STD_LOGIC;
|
signal ramwe1_s : STD_LOGIC;
|
signal ramwe2_s : STD_LOGIC;
|
signal ramwe2_s : STD_LOGIC;
|
signal memswitchrd_s : STD_LOGIC;
|
signal memswitchrd_s : STD_LOGIC;
|
signal memswitchwr_s : STD_LOGIC;
|
signal memswitchwr_s : STD_LOGIC;
|
signal reqwrfail_s : STD_LOGIC;
|
signal wmemsel_s : STD_LOGIC;
|
signal reqrdfail_s : STD_LOGIC;
|
signal rmemsel_s : STD_LOGIC;
|
signal dataready_s : STD_LOGIC;
|
signal dataready_s : STD_LOGIC;
|
signal requestwr_s : STD_LOGIC;
|
signal datareadyack_s : STD_LOGIC;
|
signal releasewr_s : STD_LOGIC;
|
|
signal requestrd_s : STD_LOGIC;
|
|
signal releaserd_s : STD_LOGIC;
|
|
|
|
begin
|
begin
|
|
|
------------------------------
|
------------------------------
|
-- 1D DCT port map
|
-- 1D DCT port map
|
| Line 359... |
Line 349... |
romodatao4 => romodatao4_s,
|
romodatao4 => romodatao4_s,
|
romodatao5 => romodatao5_s,
|
romodatao5 => romodatao5_s,
|
romodatao6 => romodatao6_s,
|
romodatao6 => romodatao6_s,
|
romodatao7 => romodatao7_s,
|
romodatao7 => romodatao7_s,
|
romodatao8 => romodatao8_s,
|
romodatao8 => romodatao8_s,
|
reqwrfail => reqwrfail_s,
|
|
|
|
ready => ready,
|
|
odv => odv1,
|
odv => odv1,
|
dcto => dcto1,
|
dcto => dcto1,
|
romeaddro0 => romeaddro0_s,
|
romeaddro0 => romeaddro0_s,
|
romeaddro1 => romeaddro1_s,
|
romeaddro1 => romeaddro1_s,
|
romeaddro2 => romeaddro2_s,
|
romeaddro2 => romeaddro2_s,
|
| Line 385... |
Line 373... |
romoaddro7 => romoaddro7_s,
|
romoaddro7 => romoaddro7_s,
|
romoaddro8 => romoaddro8_s,
|
romoaddro8 => romoaddro8_s,
|
ramwaddro => ramwaddro_s,
|
ramwaddro => ramwaddro_s,
|
ramdatai => ramdatai_s,
|
ramdatai => ramdatai_s,
|
ramwe => ramwe_s,
|
ramwe => ramwe_s,
|
requestwr => requestwr_s,
|
wmemsel => wmemsel_s
|
releasewr => releasewr_s
|
|
);
|
);
|
|
|
------------------------------
|
------------------------------
|
-- 1D DCT port map
|
-- 1D DCT port map
|
------------------------------
|
------------------------------
|
| Line 419... |
Line 406... |
romodatao7 => romo2datao7_s,
|
romodatao7 => romo2datao7_s,
|
romodatao8 => romo2datao8_s,
|
romodatao8 => romo2datao8_s,
|
romodatao9 => romo2datao9_s,
|
romodatao9 => romo2datao9_s,
|
romodatao10 => romo2datao10_s,
|
romodatao10 => romo2datao10_s,
|
ramdatao => ramdatao_s,
|
ramdatao => ramdatao_s,
|
reqrdfail => reqrdfail_s,
|
|
dataready => dataready_s,
|
dataready => dataready_s,
|
|
|
odv => odv,
|
odv => odv,
|
dcto => dcto,
|
dcto => dcto,
|
romeaddro0 => rome2addro0_s,
|
romeaddro0 => rome2addro0_s,
|
| Line 447... |
Line 433... |
romoaddro7 => romo2addro7_s,
|
romoaddro7 => romo2addro7_s,
|
romoaddro8 => romo2addro8_s,
|
romoaddro8 => romo2addro8_s,
|
romoaddro9 => romo2addro9_s,
|
romoaddro9 => romo2addro9_s,
|
romoaddro10 => romo2addro10_s,
|
romoaddro10 => romo2addro10_s,
|
ramraddro => ramraddro_s,
|
ramraddro => ramraddro_s,
|
requestrd => requestrd_s,
|
rmemsel => rmemsel_s,
|
releaserd => releaserd_s
|
datareadyack => datareadyack_s
|
);
|
);
|
|
|
------------------------------
|
------------------------------
|
-- RAM1 port map
|
-- RAM1 port map
|
------------------------------
|
------------------------------
|
| Line 491... |
Line 477... |
------------------------------
|
------------------------------
|
U_DBUFCTL : DBUFCTL
|
U_DBUFCTL : DBUFCTL
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
requestwr => requestwr_s,
|
wmemsel => wmemsel_s,
|
requestrd => requestrd_s,
|
rmemsel => rmemsel_s,
|
releasewr => releasewr_s,
|
datareadyack => datareadyack_s,
|
releaserd => releaserd_s,
|
|
|
|
memswitchwr => memswitchwr_s,
|
memswitchwr => memswitchwr_s,
|
memswitchrd => memswitchrd_s,
|
memswitchrd => memswitchrd_s,
|
reqwrfail => reqwrfail_s,
|
|
reqrdfail => reqrdfail_s,
|
|
dataready => dataready_s
|
dataready => dataready_s
|
);
|
);
|
|
|
------------------------------
|
------------------------------
|
-- ROME port map
|
-- ROME port map
|
