URL https://opencores.org/ocsvn/mdct/mdct/trunk

Subversion Repositories mdct

[/] [mdct/] [trunk/] [source/] [testbench/] [COMPILE_TIMING.DO] - Diff between revs 15 and 18

Rev 15	Rev 18
Line 23...	Line 23...
`# SIMPRIM`	`# SIMPRIM`
`set XILINX $env(XILINX)`	`set XILINX $env(XILINX)`
`vlib simprim`	`vlib simprim`
`vmap simprim simprim`	`vmap simprim simprim`

`compxlib -s mti_se -f virtex2p -l all $XILINX/vhdl/src/simprims/simprim_Vpackage_mti.vhd`	`compxlib -s mti_se -arch all -l all -lib simprim`
`compxlib -s mti_se -f virtex2p -l all $XILINX/vhdl/src/simprims/simprim_Vcomponents_mti.vhd`
`compxlib -s mti_se -f virtex2p -l all $XILINX/vhdl/src/simprims/simprim_VITAL_mti.vhd`

`vlib work`	`vlib work`
`vmap work work`	`vmap work work`

`vcom SOURCE/MDCT_PKG.vhd`	`vcom SOURCE/MDCT_PKG.vhd`
`vcom SOURCE/ROME.VHD`
`vcom SOURCE/ROMO.VHD`	`vcom SYNTHESIS/PRECISION/PROJECT_1_IMPL_1/MDCT_OUT.VHD`
`vcom SOURCE/RAM.VHD`	`vcom SOURCE/TESTBENCH/MDCTTB_PKG.VHD`
`vcom SOURCE/DCT1D.VHD`
`vcom SOURCE/DCT2D.VHD`
`vcom SOURCE/DBUFCTL.VHD`
`vcom SYNTHESIS/MDCT_TEMP_2/MDCT_OUT.VHD`
`vcom SOURCE/TESTBENCH/random1.VHD`	`vcom SOURCE/TESTBENCH/random1.VHD`
`vcom SOURCE/TESTBENCH/CLKGEN.VHD`	`vcom SOURCE/TESTBENCH/CLKGEN.VHD`
`vcom SOURCE/TESTBENCH/MDCTTB_PKG.VHD`
`vcom SOURCE/TESTBENCH/INPIMAGE.VHD`	`vcom SOURCE/TESTBENCH/INPIMAGE.VHD`
`vcom SOURCE/TESTBENCH/MDCT_TB.VHD`	`vcom SOURCE/TESTBENCH/MDCT_TB.VHD`