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https://opencores.org/ocsvn/mdct/mdct/trunk
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Rev 15 |
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Line 43... |
clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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rst : in std_logic;
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rst : in std_logic;
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dcti : in std_logic_vector(IP_W-1 downto 0);
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dcti : in std_logic_vector(IP_W-1 downto 0);
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idv : in STD_LOGIC;
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idv : in STD_LOGIC;
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ready : out STD_LOGIC; -- ready for input data
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fiforead : out STD_LOGIC; -- ready for input data
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odv : out STD_LOGIC;
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odv : out STD_LOGIC;
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dcto : out std_logic_vector(COE_W-1 downto 0);
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dcto : out std_logic_vector(COE_W-1 downto 0);
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-- debug
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-- debug
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odv1 : out STD_LOGIC;
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odv1 : out STD_LOGIC;
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dcto1 : out std_logic_vector(OP_W-1 downto 0)
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dcto1 : out std_logic_vector(OP_W-1 downto 0)
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Line 87... |
signal gate_clk_s : STD_LOGIC;
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signal gate_clk_s : STD_LOGIC;
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signal rst_s : STD_LOGIC;
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signal rst_s : STD_LOGIC;
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signal dcti_s : STD_LOGIC_VECTOR(IP_W-1 downto 0);
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signal dcti_s : STD_LOGIC_VECTOR(IP_W-1 downto 0);
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signal idv_s : STD_LOGIC;
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signal idv_s : STD_LOGIC;
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signal ready_s : STD_LOGIC;
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signal fiforead_s : STD_LOGIC;
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signal odv_s : STD_LOGIC;
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signal odv_s : STD_LOGIC;
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signal dcto_s : STD_LOGIC_VECTOR(COE_W-1 downto 0);
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signal dcto_s : STD_LOGIC_VECTOR(COE_W-1 downto 0);
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signal odv1_s : STD_LOGIC;
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signal odv1_s : STD_LOGIC;
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signal dcto1_s : STD_LOGIC_VECTOR(OP_W-1 downto 0);
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signal dcto1_s : STD_LOGIC_VECTOR(OP_W-1 downto 0);
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signal testend_s : BOOLEAN;
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signal testend_s : BOOLEAN;
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clk => clk_s,
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clk => clk_s,
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rst => rst_s,
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rst => rst_s,
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dcti => dcti_s,
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dcti => dcti_s,
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idv => idv_s,
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idv => idv_s,
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ready => ready_s,
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fiforead => fiforead_s,
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odv => odv_s,
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odv => odv_s,
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dcto => dcto_s,
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dcto => dcto_s,
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odv1 => odv1_s,
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odv1 => odv1_s,
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dcto1 => dcto1_s
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dcto1 => dcto1_s
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);
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);
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-- Input image generator
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-- Input image generator
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------------------------------
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------------------------------
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U_INPIMAGE : INPIMAGE
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U_INPIMAGE : INPIMAGE
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port map (
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port map (
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clk => clk_s,
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clk => clk_s,
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ready => ready_s,
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ready => fiforead_s,
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odv1 => odv1_s,
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odv1 => odv1_s,
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dcto1 => dcto1_s,
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dcto1 => dcto1_s,
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odv => odv_s,
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odv => odv_s,
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dcto => dcto_s,
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dcto => dcto_s,
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