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[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [sdram_models/] [16Mx16/] [mt48lc16m16a2.v] - Diff between revs 4 and 15

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Rev 4 Rev 15
Line 180... Line 180... 
        //$readmemh("bank2.txt", Bank2);
 
        //$readmemh("bank2.txt", Bank2);
 
        //$readmemh("bank3.txt", Bank3);
 
        //$readmemh("bank3.txt", Bank3);
 
        RAS_clk = 1'b0;
 
        RAS_clk = 1'b0;
 
    end
 
    end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
integer n;
 
 
 
 
 
 
 
task mem_fill;
 
 
 
input   size;
 
 
 
 
 
 
 
integer         size;
 
 
 
 
 
 
 
begin
 
 
 
        for(n=0;n<size;n=n+1)
 
 
 
           begin
 
 
 
                Bank0[n] = $random;
 
 
 
                Bank1[n] = $random;
 
 
 
                Bank2[n] = $random;
 
 
 
                Bank3[n] = $random;
 
 
 
           end
 
 
 
 
 
 
 
end
 
 
 
endtask
 
 
 
 
 
 
 
 
 
    // RAS Clk for checking tWR
 
    // RAS Clk for checking tWR
 
    always RAS_clk = #0.5 ~RAS_clk;
 
    always RAS_clk = #0.5 ~RAS_clk;
 
 
 
 
 
    // System clock generator
 
    // System clock generator
 
    always begin
 
    always begin

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