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[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [sdram_models/] [16Mx16/] [mt48lc16m16a2.v] - Diff between revs 15 and 16

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Rev 15 Rev 16
Line 210... Line 210...
    // System clock generator
    // System clock generator
    always begin
    always begin
        @ (posedge Clk) begin
        @ (posedge Clk) begin
            Sys_clk = CkeZ;
            Sys_clk = CkeZ;
            CkeZ = Cke;
            CkeZ = Cke;
 
 
            if (Cke == 1'b0 && (Data_in_enable == 1'b1 || Data_out_enable == 1'b1)) begin
            if (Cke == 1'b0 && (Data_in_enable == 1'b1 || Data_out_enable == 1'b1)) begin
                $display ("at time %t ERROR: Illegal power down or self refresh.  Please make sure data bus is idle.", $time);
                $display ("at time %t ERROR: Illegal power down or self refresh.  Please make sure data bus is idle.", $time);
            end
            end
 
 
        end
        end
        @ (negedge Clk) begin
        @ (negedge Clk) begin
            Sys_clk = 1'b0;
            Sys_clk = 1'b0;
        end
        end
    end
    end

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