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[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [test_bench_top.v] - Diff between revs 10 and 14

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Rev 10 Rev 14
Line 35... Line 35... 
////                                                             ////
 
////                                                             ////
 
/////////////////////////////////////////////////////////////////////
 
/////////////////////////////////////////////////////////////////////
 
 
 
 
 
//  CVS Log
 
//  CVS Log
 
//
 
//
 
//  $Id: test_bench_top.v,v 1.3 2001-09-02 02:29:43 rudi Exp $
 
//  $Id: test_bench_top.v,v 1.4 2001-11-11 01:52:02 rudi Exp $
 
//
 
//
 
//  $Date: 2001-09-02 02:29:43 $
 
//  $Date: 2001-11-11 01:52:02 $
 
//  $Revision: 1.3 $
 
//  $Revision: 1.4 $
 
//  $Author: rudi $
 
//  $Author: rudi $
 
//  $Locker:  $
 
//  $Locker:  $
 
//  $State: Exp $
 
//  $State: Exp $
 
//
 
//
 
// Change History:
 
// Change History:
 
//               $Log: not supported by cvs2svn $
 
//               $Log: not supported by cvs2svn $
 
 
 
//               Revision 1.3  2001/09/02 02:29:43  rudi
 
 
 
//
 
 
 
//               Fixed the TMS register setup to be tight and correct.
 
 
 
//
 
//               Revision 1.2  2001/08/10 08:16:21  rudi
 
//               Revision 1.2  2001/08/10 08:16:21  rudi
 
//
 
//
 
//               - Changed IO names to be more clear.
 
//               - Changed IO names to be more clear.
 
//               - Uniquifyed define names to be core specific.
 
//               - Uniquifyed define names to be core specific.
 
//               - Removed "Refresh Early" configuration
 
//               - Removed "Refresh Early" configuration
Line 155... Line 159... 
`define MEM_BASE2       32'h0800_0000
 
`define MEM_BASE2       32'h0800_0000
 
`define MEM_BASE3       32'h0c00_0000
 
`define MEM_BASE3       32'h0c00_0000
 
`define MEM_BASE4       32'h1000_0000
 
`define MEM_BASE4       32'h1000_0000
 
`define MEM_BASE5       32'h1400_0000
 
`define MEM_BASE5       32'h1400_0000
 
`define MEM_BASE6       32'h1800_0000
 
`define MEM_BASE6       32'h1800_0000
 
`define REG_BASE        32'hf000_0000
 
`define REG_BASE        32'h6000_0000
 
 
 
 
 
`define CSR             8'h00
 
`define CSR             8'h00
 
`define POC             8'h04
 
`define POC             8'h04
 
`define BA_MASK         8'h08
 
`define BA_MASK         8'h08
 
 
 
 
Line 211... Line 215... 
        ack_cnt = 0;
 
        ack_cnt = 0;
 
        wd_cnt = 0;
 
        wd_cnt = 0;
 
        error_cnt = 0;
 
        error_cnt = 0;
 
        clk = 1;
 
        clk = 1;
 
        mc_clk = 0;
 
        mc_clk = 0;
 
        rst = 0;
 
        rst = 1;
 
        susp_req = 0;
 
        susp_req = 0;
 
        resume_req = 0;
 
        resume_req = 0;
 
        verbose = 1;
 
        verbose = 1;
 
        mc_br = 0;
 
        mc_br = 0;
 
 
 
 
 
        repeat(11)      @(posedge clk);
 
        repeat(11)      @(posedge clk);
 
        #1;
 
        #1;
 
        rst = 1;
 
        rst = 0;
 
        repeat(10)      @(posedge clk);
 
        repeat(10)      @(posedge clk);
 
 
 
 
 
        // HERE IS WHERE THE TEST CASES GO ...
 
        // HERE IS WHERE THE TEST CASES GO ...
 
 
 
 
 
if(0)    // Full Regression Run
 
if(0)    // Full Regression Run
Line 314... Line 318... 
        sram_wr1;
 
        sram_wr1;
 
        sram_wp;
 
        sram_wp;
 
        sram_rmw1;
 
        sram_rmw1;
 
        sram_rmw2;
 
        sram_rmw2;
 
`endif
 
`endif
 
        scs_rdwr1(2);
 
        //scs_rdwr1(2);
 
 
 
 
 
 
 
        mc_reset;
 
   end
 
   end
 
else
 
//else
 
if(1)   // Suspend resume testing
 
if(1)   // Suspend resume testing
 
begin
 
begin
 
$display(" ......................................................");
 
$display(" ......................................................");
 
$display(" :                                                    :");
 
$display(" :                                                    :");
 
$display(" :    Suspend Resume Testing ...                      :");
 
$display(" :    Suspend Resume Testing ...                      :");
 
$display(" :....................................................:");
 
$display(" :....................................................:");
 
 
 
 
 
        verbose = 0;
 
        verbose = 0;
 
        done = 0;
 
        done = 0;
 
        LVL = 1;
 
        LVL = 2;
 
 
 
 
 
        fork
 
        fork
 
 
 
 
 
           begin
 
           begin
 
 
 
 
Line 372... Line 377... 
                sdram_rd5(LVL);
 
                sdram_rd5(LVL);
 
                while(susp_req | suspended)     @(posedge clk);
 
                while(susp_req | suspended)     @(posedge clk);
 
                sdram_wr5(LVL);
 
                sdram_wr5(LVL);
 
`endif
 
`endif
 
 
 
 
 
 
 
 
 
`ifdef FLASH
 
`ifdef FLASH
 
                while(susp_req | suspended)     @(posedge clk);
 
                while(susp_req | suspended)     @(posedge clk);
 
                asc_rdwr1(LVL);
 
                asc_rdwr1(LVL);
 
`endif
 
`endif
 
 
 
 
 
`ifdef SRAM
 
`ifdef SRAM
 
 
 
 
 
                while(susp_req | suspended)     @(posedge clk);
 
                while(susp_req | suspended)     @(posedge clk);
 
                sram_rd1;
 
                sram_rd1;
 
                while(susp_req | suspended)     @(posedge clk);
 
                while(susp_req | suspended)     @(posedge clk);
 
                sram_wr1;
 
                sram_wr1;
 
                while(susp_req | suspended)     @(posedge clk);
 
                while(susp_req | suspended)     @(posedge clk);
Line 394... Line 401... 
                while(susp_req | suspended)     @(posedge clk);
 
                while(susp_req | suspended)     @(posedge clk);
 
                sram_rmw1;
 
                sram_rmw1;
 
                while(susp_req | suspended)     @(posedge clk);
 
                while(susp_req | suspended)     @(posedge clk);
 
                sram_rmw2;
 
                sram_rmw2;
 
`endif
 
`endif
 
                while(susp_req | suspended)     @(posedge clk);
 
                //while(susp_req | suspended)   @(posedge clk);
 
                scs_rdwr1(LVL);
 
                //scs_rdwr1(LVL);
 
 
 
 
 
 
 
 
 
                done = 1;
 
                done = 1;
 
           end
 
           end
 
 
 
 
Line 410... Line 417... 
                        repeat(40)      @(posedge clk);
 
                        repeat(40)      @(posedge clk);
 
                        susp_res;
 
                        susp_res;
 
                   end
 
                   end
 
           end
 
           end
 
        join
 
        join
 
 
 
 
 
 
 
        mc_reset;
 
end
 
end
 
//else
 
//else
 
mc_reset;
 
if(0)    // Bus Request testing
 
 
 
 
 
if(1)   // Bus Request testing
 
 
 
begin
 
begin
 
$display(" ......................................................");
 
$display(" ......................................................");
 
$display(" :                                                    :");
 
$display(" :                                                    :");
 
$display(" :    Bus Request/Grant Testing ...                   :");
 
$display(" :    Bus Request/Grant Testing ...                   :");
 
$display(" :....................................................:");
 
$display(" :....................................................:");
 
        verbose = 0;
 
        verbose = 0;
 
        done = 0;
 
        done = 0;
 
        LVL = 1;
 
        LVL = 2;
 
        fork
 
        fork
 
 
 
 
 
           begin
 
           begin
 
`ifdef FLASH
 
`ifdef FLASH
 
                boot(LVL);
 
                boot(LVL);
Line 458... Line 465... 
                sram_wr1;
 
                sram_wr1;
 
                sram_wp;
 
                sram_wp;
 
                sram_rmw1;
 
                sram_rmw1;
 
                sram_rmw2;
 
                sram_rmw2;
 
`endif
 
`endif
 
                scs_rdwr1(LVL);
 
                //scs_rdwr1(LVL);
 
 
 
 
 
                done = 1;
 
                done = 1;
 
           end
 
           end
 
 
 
 
 
           begin
 
           begin
Line 488... Line 495... 
 
 
 
 
`define CSR             8'h00
 
`define CSR             8'h00
 
`define POC             8'h04
 
`define POC             8'h04
 
`define BA_MASK         8'h08
 
`define BA_MASK         8'h08
 
 
 
 
 
        m0.wb_wr1(`REG_BASE + `CSC3,    4'hf, 32'h0000_0000);
 
`define CSR_MASK        32'hff00_07fe
 
        //sdram_rmw2(2);
 
`define BAM_MASK        32'h0000_07ff
 
 
 
`define CSC_MASK        32'hffff_ffff
 
 
 
`define TMS_MASK        32'hffff_ffff
 
 
 
 
 
 
 
        m0.wb_wr1(`REG_BASE + `CSR,     4'hf, 32'hffff_ffff);
 
 
 
        m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'hffff_ffff);
 
 
 
        m0.wb_wr1(`REG_BASE + `CSC0,    4'hf, 32'hffff_ffff);
 
 
 
        m0.wb_wr1(`REG_BASE + `TMS0,    4'hf, 32'hffff_ffff);
 
 
 
        m0.wb_wr1(`REG_BASE + `CSC1,    4'hf, 32'hffff_ffff);
 
 
 
        m0.wb_wr1(`REG_BASE + `TMS1,    4'hf, 32'hffff_ffff);
 
 
 
        m0.wb_wr1(`REG_BASE + `CSC2,    4'hf, 32'hffff_ffff);
 
 
 
        m0.wb_wr1(`REG_BASE + `TMS2,    4'hf, 32'hffff_ffff);
 
 
 
        m0.wb_wr1(`REG_BASE + `CSC3,    4'hf, 32'hffff_ffff);
 
 
 
        m0.wb_wr1(`REG_BASE + `TMS3,    4'hf, 32'hffff_ffff);
 
 
 
 
 
 
 
        m0.wb_rd1(`REG_BASE + `CSR,     4'hf, data);
 
 
 
        m0.wb_rd1(`REG_BASE + `BA_MASK, 4'hf, data);
 
 
 
        m0.wb_rd1(`REG_BASE + `CSC0,    4'hf, data);
 
 
 
        m0.wb_rd1(`REG_BASE + `TMS0,    4'hf, data);
 
 
 
        m0.wb_rd1(`REG_BASE + `CSC1,    4'hf, data);
 
 
 
        m0.wb_rd1(`REG_BASE + `TMS1,    4'hf, data);
 
 
 
        m0.wb_rd1(`REG_BASE + `CSC2,    4'hf, data);
 
 
 
        m0.wb_rd1(`REG_BASE + `TMS2,    4'hf, data);
 
 
 
        m0.wb_rd1(`REG_BASE + `CSC3,    4'hf, data);
 
 
 
        m0.wb_rd1(`REG_BASE + `TMS3,    4'hf, data);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
        m0.wb_wr1(`REG_BASE + `CSC3,    4'hf, 32'h0000_0000);
 
 
 
        //sdram_rd1(2);
 
 
 
        //sdram_wr1(2);
 
 
 
        //asc_rdwr1(2);
 
        //sram_rd1;
 
        //sram_rd1;
 
 
 
        //sram_wr1;
 
        //sram_rmw1;
 
        //sram_rmw1;
 
        //sram_rmw2;
 
        //sram_rmw2;
 
        //sram_wp;
 
        //sram_wp;
 
 
 
 
 
        //scs_rdwr1(2);
 
        //scs_rdwr1(2);
 
 
 
 
 
 
 
 
 
        //sdram_rd3(2);
 
 
 
        //sdram_wr3(2);
 
 
 
 
 
 
 
        //asc_rdwr1(2);
 
        //asc_rdwr1(2);
 
        //asc_rdwr1_x(2);
 
        //asc_rdwr1_x(2);
 
 
 
 
 
        //sdram_wp(2);
 
        //sdram_wp(2);
 
        //sdram_rmw1(2);
 
        //sdram_rmw1(2);
 
        //sdram_rmw2(2);
 
        //sdram_rmw2(2);
 
 
 
 
 
        //sdram_rd2(2);
 
        //sdram_rd2(2);
 
        //sdram_wr2(2);
 
        //sdram_wr2(2);
 
        sdram_wr1(2);
 
 
 
 
 
        //sdram_bo;
 
 
 
        //sdram_rd1b(2);
 
 
 
 
 
 
 
        //sdram_rd1(2);
 
 
 
        //sdram_wr1(2);
 
 
 
 
 
 
 
        //sdram_rd5(2);
 
 
 
        //sdram_wr5(2);
 
/*
 
/*
 
        sdram_rd1(2);
 
        sdram_rd1(2);
 
        sdram_wr1(2);
 
        sdram_wr1(2);
 
        sdram_rd2(2);
 
        sdram_rd2(2);
 
        sdram_wr2(2);
 
        sdram_wr2(2);
 
        sdram_rd3(2);
 
        sdram_rd3(2);
 
        sdram_wr3(2);
 
        sdram_wr3(2);
 
        sdram_rd4(2);
 
        sdram_rd4(2);
 
        sdram_wr4(2);
 
        sdram_wr4(2);
 
 
 
 
 
        sdram_rd5(2);
 
        sdram_rd5(2);
 
        sdram_wr5(2);
 
        sdram_wr5(2);
 
 
 
 
 
        sdram_wp(2);
 
        sdram_wp(2);
 
        sdram_rmw1(2);
 
        sdram_rmw1(2);
 
        sdram_rmw2(2);
 
        sdram_rmw2(2);
 
 
 
 
 
*/
 
*/
 
 
 
 
 
        //sdram_rmw2(2);
 
 
 
 
 
 
 
        repeat(100)     @(posedge clk);
 
        repeat(100)     @(posedge clk);
 
        $finish;
 
        $finish;
 
   end
 
   end
 
else
 
else
Line 567... Line 611... 
//
 
//
 
 
 
 
 
always #2.5     clk = ~clk;
 
always #2.5     clk = ~clk;
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        //#0.5 mc_clk <= ~mc_clk;
 
 
 
        //#4.5 mc_clk <= ~mc_clk;
 
 
 
        mc_clk <= ~mc_clk;
 
        mc_clk <= ~mc_clk;
 
 
 
 
 
/////////////////////////////////////////////////////////////////////
 
/////////////////////////////////////////////////////////////////////
 
//
 
//
 
// IO Monitors
 
// IO Monitors
Line 658... Line 700... 
           2: rst_dq_val = {28'hzzz_zzzz, 2'b10, 2'b10};
 
           2: rst_dq_val = {28'hzzz_zzzz, 2'b10, 2'b10};
 
         //  3: rst_dq_val = {28'hzzzz_zzzz, 2'b10, 2'b11};
 
         //  3: rst_dq_val = {28'hzzzz_zzzz, 2'b10, 2'b11};
 
           default: rst_dq_val = 32'hzzzz_zzzz;
 
           default: rst_dq_val = 32'hzzzz_zzzz;
 
        endcase
 
        endcase
 
 
 
 
 
assign #1 mc_dq = mc_data_oe ? mc_data_o : (~rst ? rst_dq_val : 32'hzzzz_zzzz);
 
/*
 
assign #1 mc_data_i = mc_dq;
 
assign #1 mc_dq = mc_data_oe ? mc_data_o : (rst ? rst_dq_val : 32'hzzzz_zzzz);
 
 
 
assign #1 mc_data_i = mc_dq;
 
 
 
 
 
 
 
assign #1 mc_dqp = mc_data_oe ? mc_dp_o : 4'hz;
 
 
 
assign #1 mc_dp_i = mc_dqp;
 
 
 
 
 
 
 
assign #1 mc_addr = mc_c_oe ? _mc_addr : 24'bz;
 
 
 
assign #1 mc_dqm = mc_c_oe ? _mc_dqm : 4'bz;
 
 
 
assign #1 mc_oe_ = mc_c_oe ? _mc_oe_ : 1'bz;
 
 
 
assign #1 mc_we_ = mc_c_oe ? _mc_we_ : 1'bz;
 
 
 
assign #1 mc_cas_ = mc_c_oe ? _mc_cas_ : 1'bz;
 
 
 
assign #1 mc_ras_ = mc_c_oe ? _mc_ras_ : 1'bz;
 
 
 
assign #1 mc_cke_ = mc_c_oe ? _mc_cke_ : 1'bz;
 
 
 
assign #1 mc_cs_ = mc_c_oe ? _mc_cs_ : 8'bz;
 
 
 
assign #1 mc_rp_ = mc_c_oe ? _mc_rp_ : 1'bz;
 
 
 
assign #1 mc_vpen = mc_c_oe ? _mc_vpen : 1'bz;
 
 
 
assign #1 mc_adsc_ = mc_c_oe ? _mc_adsc_ : 1'bz;
 
 
 
assign #1 mc_adv_ = mc_c_oe ? _mc_adv_ : 1'bz;
 
 
 
assign #1 mc_zz = mc_c_oe ? _mc_zz : 1'bz;
 
 
 
*/
 
 
 
 
 
 
 
 
 
 
 
assign  mc_dq = mc_data_oe ? mc_data_o : (rst ? rst_dq_val : 32'hzzzz_zzzz);
 
 
 
assign  mc_data_i = mc_dq;
 
 
 
 
 
 
 
assign  mc_dqp = mc_data_oe ? mc_dp_o : 4'hz;
 
 
 
assign  mc_dp_i = mc_dqp;
 
 
 
 
 
 
 
assign  mc_addr = mc_c_oe ? _mc_addr : 24'bz;
 
 
 
assign  mc_dqm = mc_c_oe ? _mc_dqm : 4'bz;
 
 
 
assign  mc_oe_ = mc_c_oe ? _mc_oe_ : 1'bz;
 
 
 
assign  mc_we_ = mc_c_oe ? _mc_we_ : 1'bz;
 
 
 
assign  mc_cas_ = mc_c_oe ? _mc_cas_ : 1'bz;
 
 
 
assign  mc_ras_ = mc_c_oe ? _mc_ras_ : 1'bz;
 
 
 
assign  #1.5 mc_cke_ = mc_c_oe ? _mc_cke_ : 1'bz;
 
 
 
assign  mc_cs_ = mc_c_oe ? _mc_cs_ : 8'bz;
 
 
 
assign  mc_rp_ = mc_c_oe ? _mc_rp_ : 1'bz;
 
 
 
assign  mc_vpen = mc_c_oe ? _mc_vpen : 1'bz;
 
 
 
assign  mc_adsc_ = mc_c_oe ? _mc_adsc_ : 1'bz;
 
 
 
assign  mc_adv_ = mc_c_oe ? _mc_adv_ : 1'bz;
 
 
 
assign  mc_zz = mc_c_oe ? _mc_zz : 1'bz;
 
 
 
 
 
 
 
 
 
assign #1 mc_dqp = mc_data_oe ? mc_dp_o : 4'hz;
 
 
 
assign #1 mc_dp_i = mc_dqp;
 
 
 
 
 
 
 
assign #1 mc_addr = mc_c_oe ? _mc_addr : 24'bz;
 
 
 
assign #1 mc_dqm = mc_c_oe ? _mc_dqm : 4'bz;
 
 
 
assign #1 mc_oe_ = mc_c_oe ? _mc_oe_ : 1'bz;
 
 
 
assign #1 mc_we_ = mc_c_oe ? _mc_we_ : 1'bz;
 
 
 
assign #1 mc_cas_ = mc_c_oe ? _mc_cas_ : 1'bz;
 
 
 
assign #1 mc_ras_ = mc_c_oe ? _mc_ras_ : 1'bz;
 
 
 
assign #1 mc_cke_ = mc_c_oe ? _mc_cke_ : 1'bz;
 
 
 
assign #1 mc_cs_ = mc_c_oe ? _mc_cs_ : 8'bz;
 
 
 
assign #1 mc_rp_ = mc_c_oe ? _mc_rp_ : 1'bz;
 
 
 
assign #1 mc_vpen = mc_c_oe ? _mc_vpen : 1'bz;
 
 
 
assign #1 mc_adsc_ = mc_c_oe ? _mc_adsc_ : 1'bz;
 
 
 
assign #1 mc_adv_ = mc_c_oe ? _mc_adv_ : 1'bz;
 
 
 
assign #1 mc_zz = mc_c_oe ? _mc_zz : 1'bz;
 
 
 
 
 
 
 
pullup p0(mc_cas_);
 
pullup p0(mc_cas_);
 
pullup p1(mc_ras_);
 
pullup p1(mc_ras_);
 
pullup p2(mc_oe_);
 
pullup p2(mc_oe_);
 
pullup p3(mc_we_);
 
pullup p3(mc_we_);
Line 748... Line 816... 
//
 
//
 
// WISHBONE Master Model
 
// WISHBONE Master Model
 
//
 
//
 
 
 
 
 
wb_mast m0(     .clk(           clk             ),
 
wb_mast m0(     .clk(           clk             ),
 
                .rst(           rst             ),
 
                .rst(           ~rst            ),
 
                .adr(           wb_addr_i       ),
 
                .adr(           wb_addr_i       ),
 
                .din(           wb_data_o       ),
 
                .din(           wb_data_o       ),
 
                .dout(          wb_data_i       ),
 
                .dout(          wb_data_i       ),
 
                .cyc(           wb_cyc_i        ),
 
                .cyc(           wb_cyc_i        ),
 
                .stb(           wb_stb_i        ),
 
                .stb(           wb_stb_i        ),
Line 871... Line 939... 
                .We_n(          mc_we_          ),
 
                .We_n(          mc_we_          ),
 
                .Dqm(           mc_dqm          )
 
                .Dqm(           mc_dqm          )
 
                );
 
                );
 
 
 
 
 
 
 
 
 
/*
 
mt48lc16m16a2 sdram1a(
 
 
 
                .Dq(            mc_dq[15:0]      ),
 
mt48lc4m16a2 sdram1a(
 
                .Addr(          mc_addr[12:0]    ),
 
                .Dq(            mc_dq[15:0]     ),
 
                .Ba(            mc_addr[14:13]  ),
 
                .Addr(          mc_addr[11:0]   ),
 
                .Clk(           mc_clk          ),
 
                .Ba(            mc_addr[14:13]  ),
 
                .Cke(           mc_cke_         ),
 
                .Clk(           mc_clk          ),
 
                .Cs_n(          mc_cs_[5]       ),
 
                .Cke(           mc_cke_         ),
 
                .Ras_n(         mc_ras_         ),
 
                .Cs_n(          mc_cs_[1]       ),
 
                .Cas_n(         mc_cas_         ),
 
                .Ras_n(         mc_ras_         ),
 
                .We_n(          mc_we_          ),
 
                .Cas_n(         mc_cas_         ),
 
                .Dqm(           mc_dqm[1:0]      )
 
                .We_n(          mc_we_          ),
 
                );
 
                .Dqm(           mc_dqm[1:0]     )
 
 
 
                );
 
 
 
 
 
 
 
mt48lc4m16a2 sdram1b(
 
mt48lc16m16a2 sdram1b(
 
                .Dq(            mc_dq[31:16]    ),
 
                .Dq(            mc_dq[31:16]    ),
 
                .Addr(          mc_addr[11:0]   ),
 
                .Addr(          mc_addr[12:0]    ),
 
                .Ba(            mc_addr[14:13]  ),
 
                .Ba(            mc_addr[14:13]  ),
 
                .Clk(           mc_clk          ),
 
                .Clk(           mc_clk          ),
 
                .Cke(           mc_cke_         ),
 
                .Cke(           mc_cke_         ),
 
                .Cs_n(          mc_cs_[1]       ),
 
                .Cs_n(          mc_cs_[5]       ),
 
                .Ras_n(         mc_ras_         ),
 
                .Ras_n(         mc_ras_         ),
 
                .Cas_n(         mc_cas_         ),
 
                .Cas_n(         mc_cas_         ),
 
                .We_n(          mc_we_          ),
 
                .We_n(          mc_we_          ),
 
                .Dqm(           mc_dqm[3:2]     )
 
                .Dqm(           mc_dqm[3:2]     )
 
                );
 
                );
 
 
 
 
 
 
 
/*
 
mt48lc8m8a2 sdram2a(
 
mt48lc8m8a2 sdram2a(
 
                .Dq(            mc_dq[07:00]    ),
 
                .Dq(            mc_dq[07:00]    ),
 
                .Addr(          mc_addr[11:0]   ),
 
                .Addr(          mc_addr[11:0]   ),
 
                .Ba(            mc_addr[14:13]  ),
 
                .Ba(            mc_addr[14:13]  ),
 
                .Clk(           mc_clk          ),
 
                .Clk(           mc_clk          ),

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