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[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [test_bench_top.v] - Diff between revs 14 and 15

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Rev 14 Rev 15
Line 35... Line 35... 
////                                                             ////
 
////                                                             ////
 
/////////////////////////////////////////////////////////////////////
 
/////////////////////////////////////////////////////////////////////
 
 
 
 
 
//  CVS Log
 
//  CVS Log
 
//
 
//
 
//  $Id: test_bench_top.v,v 1.4 2001-11-11 01:52:02 rudi Exp $
 
//  $Id: test_bench_top.v,v 1.5 2001-11-13 00:45:15 rudi Exp $
 
//
 
//
 
//  $Date: 2001-11-11 01:52:02 $
 
//  $Date: 2001-11-13 00:45:15 $
 
//  $Revision: 1.4 $
 
//  $Revision: 1.5 $
 
//  $Author: rudi $
 
//  $Author: rudi $
 
//  $Locker:  $
 
//  $Locker:  $
 
//  $State: Exp $
 
//  $State: Exp $
 
//
 
//
 
// Change History:
 
// Change History:
 
//               $Log: not supported by cvs2svn $
 
//               $Log: not supported by cvs2svn $
 
 
 
//               Revision 1.4  2001/11/11 01:52:02  rudi
 
 
 
//
 
 
 
//               Minor fixes to testbench ...
 
 
 
//
 
//               Revision 1.3  2001/09/02 02:29:43  rudi
 
//               Revision 1.3  2001/09/02 02:29:43  rudi
 
//
 
//
 
//               Fixed the TMS register setup to be tight and correct.
 
//               Fixed the TMS register setup to be tight and correct.
 
//
 
//
 
//               Revision 1.2  2001/08/10 08:16:21  rudi
 
//               Revision 1.2  2001/08/10 08:16:21  rudi
Line 228... Line 232... 
        rst = 0;
 
        rst = 0;
 
        repeat(10)      @(posedge clk);
 
        repeat(10)      @(posedge clk);
 
 
 
 
 
        // HERE IS WHERE THE TEST CASES GO ...
 
        // HERE IS WHERE THE TEST CASES GO ...
 
 
 
 
 
if(0)    // Full Regression Run
 
if(1)   // Full Regression Run
 
   begin
 
   begin
 
$display(" ......................................................");
 
$display(" ......................................................");
 
$display(" :                                                    :");
 
$display(" :                                                    :");
 
$display(" :    Long Regression Run ...                         :");
 
$display(" :    Long Regression Run ...                         :");
 
$display(" :....................................................:");
 
$display(" :....................................................:");
Line 273... Line 277... 
 
 
 
 
        scs_rdwr1(0);
 
        scs_rdwr1(0);
 
 
 
 
 
   end
 
   end
 
else
 
else
 
if(0)    // Quick Regression Run
 
if(1)   // Quick Regression Run
 
   begin
 
   begin
 
$display(" ......................................................");
 
$display(" ......................................................");
 
$display(" :                                                    :");
 
$display(" :                                                    :");
 
$display(" :    Short Regression Run ...                        :");
 
$display(" :    Short Regression Run ...                        :");
 
$display(" :....................................................:");
 
$display(" :....................................................:");
Line 421... Line 425... 
        join
 
        join
 
 
 
 
 
        mc_reset;
 
        mc_reset;
 
end
 
end
 
//else
 
//else
 
if(0)    // Bus Request testing
 
if(1)   // Bus Request testing
 
begin
 
begin
 
$display(" ......................................................");
 
$display(" ......................................................");
 
$display(" :                                                    :");
 
$display(" :                                                    :");
 
$display(" :    Bus Request/Grant Testing ...                   :");
 
$display(" :    Bus Request/Grant Testing ...                   :");
 
$display(" :....................................................:");
 
$display(" :....................................................:");
Line 490... Line 494... 
$display(" :                                                    :");
 
$display(" :                                                    :");
 
$display(" :    Test Debug Testing ...                          :");
 
$display(" :    Test Debug Testing ...                          :");
 
$display(" :....................................................:");
 
$display(" :....................................................:");
 
        //verbose = 0;
 
        //verbose = 0;
 
        //boot(2);
 
        //boot(2);
 
 
 
/*
 
 
 
 
 
`define CSR             8'h00
 
`define CSR             8'h00
 
`define POC             8'h04
 
`define POC             8'h04
 
`define BA_MASK         8'h08
 
`define BA_MASK         8'h08
 
 
 
 
 
`define CSR_MASK        32'hff00_07fe
 
`define CSR_MASK        32'hff00_07fe
 
`define BAM_MASK        32'h0000_07ff
 
`define BAM_MASK        32'h0000_07ff
 
`define CSC_MASK        32'hffff_ffff
 
`define CSC_MASK        32'hffff_ffff
 
`define TMS_MASK        32'hffff_ffff
 
`define TMS_MASK        32'hffff_ffff
 
 
 
 
 
        m0.wb_wr1(`REG_BASE + `CSR,     4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `CSR,     4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `CSC0,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `CSC0,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `TMS0,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `TMS0,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `CSC1,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `CSC1,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `TMS1,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `TMS1,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `CSC2,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `CSC2,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `TMS2,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `TMS2,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `CSC3,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `CSC3,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `TMS3,    4'hf, 32'hffff_ffff);
 
        m0.wb_wr1(`REG_BASE + `TMS3,    4'hf, 32'hffff_ffff);
 
 
 
 
 
        m0.wb_rd1(`REG_BASE + `CSR,     4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `CSR,     4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `BA_MASK, 4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `BA_MASK, 4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `CSC0,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `CSC0,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `TMS0,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `TMS0,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `CSC1,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `CSC1,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `TMS1,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `TMS1,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `CSC2,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `CSC2,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `TMS2,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `TMS2,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `CSC3,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `CSC3,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `TMS3,    4'hf, data);
 
        m0.wb_rd1(`REG_BASE + `TMS3,    4'hf, data);
 
 
 
*/
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
        m0.wb_wr1(`REG_BASE + `CSC3,    4'hf, 32'h0000_0000);
 
        m0.wb_wr1(`REG_BASE + `CSC3,    4'hf, 32'h0000_0000);
Line 556... Line 561... 
        //sdram_rd1(2);
 
        //sdram_rd1(2);
 
        //sdram_wr1(2);
 
        //sdram_wr1(2);
 
 
 
 
 
        //sdram_rd5(2);
 
        //sdram_rd5(2);
 
        //sdram_wr5(2);
 
        //sdram_wr5(2);
 
 
 
        sdram_wr4(2);
 
/*
 
/*
 
        sdram_rd1(2);
 
        sdram_rd1(2);
 
        sdram_wr1(2);
 
        sdram_wr1(2);
 
        sdram_rd2(2);
 
        sdram_rd2(2);
 
        sdram_wr2(2);
 
        sdram_wr2(2);

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