URL https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk

Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [tests.v] - Diff between revs 4 and 8

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 4	Rev 8
Line 35...	Line 35...
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: tests.v,v 1.1 2001-07-29 07:34:40 rudi Exp $`	`// $Id: tests.v,v 1.2 2001-08-10 08:16:21 rudi Exp $`
`//`	`//`
`// $Date: 2001-07-29 07:34:40 $`	`// $Date: 2001-08-10 08:16:21 $`
`// $Revision: 1.1 $`	`// $Revision: 1.2 $`
`// $Author: rudi $`	`// $Author: rudi $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2001/07/29 07:34:40 rudi`
	`//`
	`//`
	`// 1) Changed Directory Structure`
	`// 2) Fixed several minor bugs`
	`//`
`// Revision 1.1.1.1 2001/05/13 09:36:38 rudi`	`// Revision 1.1.1.1 2001/05/13 09:36:38 rudi`
`// Created Directory Structure`	`// Created Directory Structure`
`//`	`//`
`//`	`//`
`//`	`//`
Line 96...	Line 102...
`0: del_max = 16;`	`0: del_max = 16;`
`1: del_max = 8;`	`1: del_max = 8;`
`2: del_max = 4;`	`2: del_max = 4;`
`endcase`	`endcase`

`size = 4;`	`size = 8;`
`del = 0;`	`del = 0;`
`mode = 0;`	`mode = 8;`
`write = 1;`	`write = 1;`
`//force sdram0.Debug = 1;`	`//force sdram0.Debug = 1;`

`for(mode=0;mode<10;mode=mode+1)`	`for(mode=0;mode<10;mode=mode+1)`
`begin`	`begin`
Line 2245...	Line 2251...


`task sram_rd1;`	`task sram_rd1;`

`integer n,m,read,write;`	`integer n,m,read,write;`
`integer del, size;`	`integer d2, del, size;`
`reg [31:0] data;`	`reg [31:0] data;`
`begin`	`begin`

`$display("\n\n");`	`$display("\n\n");`
`$display("*****************************************************");`	`$display("*****************************************************");`
Line 2260...	Line 2266...
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);	m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);

m0.wb_wr1(`REG_BASE + `TMS4, 4'hf, 32'hffff_ffff);	m0.wb_wr1(`REG_BASE + `TMS4, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `CSC4, 4'hf, 32'h0080_0003);	m0.wb_wr1(`REG_BASE + `CSC4, 4'hf, 32'h0080_0003);

`size = 1;`	`size = 4;`
`del = 0;`	`del = 0;`
`read = 1;`	`read = 1;`
`write = 0;`	`write = 0;`

`sram0a.mem_fill( 256 );`	`sram0a.mem_fill( 256 );`
Line 3008...	Line 3014...
`begin`	`begin`
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821 \| (kro[0]<<10));	m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821 \| (kro[0]<<10));

`size = 4;`	`size = 4;`
`del = 2;`	`del = 2;`
`mode = 7;`	`mode = 9;`

`//force sdram0.Debug = 1;`	`//force sdram0.Debug = 1;`

`for(mode=0;mode<10;mode=mode+1)`	`for(mode=0;mode<10;mode=mode+1)`
`begin`	`begin`

Browse

Tools

Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [tests.v] - Diff between revs 4 and 8