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[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [wb_mast_model.v] - Diff between revs 14 and 16

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Line 11... Line 11... 
////                                                             ////
 
////                                                             ////
 
/////////////////////////////////////////////////////////////////////
 
/////////////////////////////////////////////////////////////////////
 
////                                                             ////
 
////                                                             ////
 
//// Copyright (C) 2000 Rudolf Usselmann                         ////
 
//// Copyright (C) 2000 Rudolf Usselmann                         ////
 
////                    rudi@asics.ws                            ////
 
////                    rudi@asics.ws                            ////
 
////                                                             ////
 
///                                                             ////
 
//// This source file may be used and distributed without        ////
 
//// This source file may be used and distributed without        ////
 
//// restriction provided that this copyright statement is not   ////
 
//// restriction provided that this copyright statement is not   ////
 
//// removed from the file and that any derivative work contains ////
 
//// removed from the file and that any derivative work contains ////
 
//// the original copyright notice and the associated disclaimer.////
 
//// the original copyright notice and the associated disclaimer.////
 
////                                                             ////
 
////                                                             ////
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////                                                             ////
 
////                                                             ////
 
/////////////////////////////////////////////////////////////////////
 
/////////////////////////////////////////////////////////////////////
 
 
 
 
 
//  CVS Log
 
//  CVS Log
 
//
 
//
 
//  $Id: wb_mast_model.v,v 1.2 2001-11-11 01:52:03 rudi Exp $
 
//  $Id: wb_mast_model.v,v 1.3 2001-11-29 02:17:36 rudi Exp $
 
//
 
//
 
//  $Date: 2001-11-11 01:52:03 $
 
//  $Date: 2001-11-29 02:17:36 $
 
//  $Revision: 1.2 $
 
//  $Revision: 1.3 $
 
//  $Author: rudi $
 
//  $Author: rudi $
 
//  $Locker:  $
 
//  $Locker:  $
 
//  $State: Exp $
 
//  $State: Exp $
 
//
 
//
 
// Change History:
 
// Change History:
 
//               $Log: not supported by cvs2svn $
 
//               $Log: not supported by cvs2svn $
 
 
 
//               Revision 1.2  2001/11/11 01:52:03  rudi
 
 
 
//
 
 
 
//               Minor fixes to testbench ...
 
 
 
//
 
//               Revision 1.1  2001/07/29 07:34:40  rudi
 
//               Revision 1.1  2001/07/29 07:34:40  rudi
 
//
 
//
 
//
 
//
 
//               1) Changed Directory Structure
 
//               1) Changed Directory Structure
 
//               2) Fixed several minor bugs
 
//               2) Fixed several minor bugs
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input           wcount;
 
input           wcount;
 
 
 
 
 
integer         delay;
 
integer         delay;
 
integer         rcount;
 
integer         rcount;
 
integer         wcount;
 
integer         wcount;
 
 
 
 
 
 
 
begin
 
 
 
wb_rmw2(a,a,s,delay,rcount,wcount);
 
 
 
end
 
 
 
endtask
 
 
 
 
 
 
 
 
 
 
 
task wb_rmw2;
 
 
 
input   [31:0]   ra;
 
 
 
input   [31:0]   wa;
 
 
 
input   [3:0]    s;
 
 
 
input           delay;
 
 
 
input           rcount;
 
 
 
input           wcount;
 
 
 
 
 
 
 
integer         delay;
 
 
 
integer         rcount;
 
 
 
integer         wcount;
 
integer         n;
 
integer         n;
 
 
 
 
 
begin
 
begin
 
 
 
 
 
@(posedge clk);
 
//@(posedge clk);
 
#1;
 
#1;
 
cyc = 1;
 
cyc = 1;
 
we = 0;
 
we = 0;
 
sel = s;
 
sel = s;
 
repeat(delay)   @(posedge clk);
 
repeat(delay)   @(posedge clk);
 
 
 
 
 
for(n=0;n<rcount-1;n=n+1)
 
for(n=0;n<rcount-1;n=n+1)
 
   begin
 
   begin
 
        adr = a + (n*4);
 
        adr = ra + (n*4);
 
        stb = 1;
 
        stb = 1;
 
        while(~ack & ~err)      @(posedge clk);
 
        while(~ack & ~err)      @(posedge clk);
 
        rd_mem[n + rd_cnt] = din;
 
        rd_mem[n + rd_cnt] = din;
 
        //$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
 
        //$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
 
        #2;
 
        #2;
Line 350... Line 372... 
           end
 
           end
 
        we = 0;
 
        we = 0;
 
        sel = s;
 
        sel = s;
 
   end
 
   end
 
 
 
 
 
adr = a+(n*4);
 
adr = ra+(n*4);
 
stb = 1;
 
stb = 1;
 
@(posedge clk);
 
@(posedge clk);
 
while(~ack & ~err)      @(posedge clk);
 
while(~ack & ~err)      @(posedge clk);
 
rd_mem[n + rd_cnt] = din;
 
rd_mem[n + rd_cnt] = din;
 
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
 
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
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        repeat(delay)
 
        repeat(delay)
 
           begin
 
           begin
 
                @(posedge clk);
 
                @(posedge clk);
 
                #1;
 
                #1;
 
           end
 
           end
 
        adr = a + (n*4);
 
        adr = wa + (n*4);
 
        dout = wr_mem[n + wr_cnt];
 
        dout = wr_mem[n + wr_cnt];
 
        stb = 1;
 
        stb = 1;
 
        we=1;
 
        we=1;
 
        sel = s;
 
        sel = s;
 
//      if(n!=0)
 
//      if(n!=0)
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integer         wcount;
 
integer         wcount;
 
integer         n;
 
integer         n;
 
 
 
 
 
begin
 
begin
 
 
 
 
 
@(posedge clk);
 
//@(posedge clk);
 
#1;
 
#1;
 
cyc = 1;
 
cyc = 1;
 
we = 1'bx;
 
we = 1'bx;
 
sel = 4'hx;
 
sel = 4'hx;
 
sel = s;
 
sel = s;

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