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https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk
[/] [mem_ctrl/] [trunk/] [doc/] [README.txt] - Diff between revs 4 and 7
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http://www.opencores.org/cores/mem_ctrl
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http://www.opencores.org/cores/mem_ctrl
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To find out more about me (Rudolf Usselmann), please visit:
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To find out more about me (Rudolf Usselmann), please visit:
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http://www.asics.ws
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http://www.asics.ws
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Directory Structure
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[core_root]
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+-doc Documentation
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+-bench--+ Test Bench
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| +- verilog Verilog Sources
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| +-vhdl VHDL Sources
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+-rtl----+ Core RTL Sources
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| +-verilog Verilog Sources
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| +-vhdl VHDL Sources
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+-sim----+
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| +-rtl_sim---+ Functional verification Directory
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| | +-bin Makefiles/Run Scripts
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| | +-run Working Directory
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| +-gate_sim--+ Functional & Timing Gate Level
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| | Verification Directory
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| +-bin Makefiles/Run Scripts
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| +-run Working Directory
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+-lint--+ Lint Directory Tree
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| +-bin Makefiles/Run Scripts
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| +-run Working Directory
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| +-log Linter log & result files
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+-syn---+ Synthesis Directory Tree
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| +-bin Synthesis Scripts
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| +-run Working Directory
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| +-log Synthesis log files
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| +-out Synthesis Output
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