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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_adr_sel.v,v 1.2 2001-08-10 08:16:21 rudi Exp $
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// $Id: mc_adr_sel.v,v 1.3 2001-11-29 02:16:28 rudi Exp $
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//
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//
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// $Date: 2001-08-10 08:16:21 $
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// $Date: 2001-11-29 02:16:28 $
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// $Revision: 1.2 $
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// $Revision: 1.3 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/08/10 08:16:21 rudi
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//
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Removed "Refresh Early" configuration
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//
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// Revision 1.1 2001/07/29 07:34:41 rudi
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// Revision 1.1 2001/07/29 07:34:41 rudi
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//
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//
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//
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//
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// 1) Changed Directory Structure
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// 1) Changed Directory Structure
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// 2) Fixed several minor bugs
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// 2) Fixed several minor bugs
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//
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//
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//
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//
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`include "mc_defines.v"
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`include "mc_defines.v"
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module mc_adr_sel(clk, csc, tms, wb_ack_o, wb_stb_i, wb_addr_i,
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module mc_adr_sel(clk, csc, tms, wb_ack_o, wb_stb_i, wb_addr_i, wb_we_i,
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wb_write_go, wr_hold, cas_,
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wb_write_go, wr_hold, cas_,
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mc_addr, row_adr, bank_adr, rfr_ack,
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mc_addr, row_adr, bank_adr, rfr_ack,
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cs_le, cmd_a10, row_sel, lmr_sel, next_adr, wr_cycle,
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cs_le, cmd_a10, row_sel, lmr_sel, next_adr, wr_cycle,
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page_size);
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page_size);
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input clk;
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input clk;
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input [31:0] csc;
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input [31:0] csc;
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input [31:0] tms;
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input [31:0] tms;
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input wb_ack_o, wb_stb_i;
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input wb_ack_o, wb_stb_i;
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input [31:0] wb_addr_i;
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input [31:0] wb_addr_i;
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input wb_we_i;
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input wb_write_go;
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input wb_write_go;
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input wr_hold;
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input wr_hold;
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input cas_;
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input cas_;
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output [23:0] mc_addr;
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output [23:0] mc_addr;
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output [12:0] row_adr;
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output [12:0] row_adr;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Async Devices Address Latch & Counter
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// Async Devices Address Latch & Counter
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//
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//
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//assign asc_addr_pl1 = asc_addr + 1;
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mc_incn_r #(24) u0( .clk( clk ),
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mc_incn_r #(24) u0( .clk( clk ),
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.inc_in( acs_addr ),
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.inc_in( acs_addr ),
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.inc_out( acs_addr_pl1 ) );
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.inc_out( acs_addr_pl1 ) );
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always @(posedge clk)
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always @(posedge clk)
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if(wb_stb_i) sram_addr <= #1 wb_addr_i[25:2];
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if(wb_stb_i) sram_addr <= #1 wb_addr_i[25:2];
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always @(posedge clk)
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always @(posedge clk)
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// *** Use same address for write and read ***
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if(cs_le | wb_we_i)
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//if(wb_write_go) acs_addr <= #1 wb_addr_i[25:2];
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//else
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if(cs_le)
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case(bus_width) // synopsys full_case parallel_case
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case(bus_width) // synopsys full_case parallel_case
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`MC_BW_8: acs_addr <= #1 wb_addr_i[23:0];
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`MC_BW_8: acs_addr <= #1 wb_addr_i[23:0];
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`MC_BW_16: acs_addr <= #1 wb_addr_i[24:1];
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`MC_BW_16: acs_addr <= #1 wb_addr_i[24:1];
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`MC_BW_32: acs_addr <= #1 wb_addr_i[25:2];
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`MC_BW_32: acs_addr <= #1 wb_addr_i[25:2];
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endcase
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endcase
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