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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_adr_sel.v,v 1.1 2001-07-29 07:34:41 rudi Exp $
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// $Id: mc_adr_sel.v,v 1.2 2001-08-10 08:16:21 rudi Exp $
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//
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//
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// $Date: 2001-07-29 07:34:41 $
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// $Date: 2001-08-10 08:16:21 $
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// $Revision: 1.1 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/07/29 07:34:41 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Fixed several minor bugs
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//
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// Revision 1.2 2001/06/12 15:19:49 rudi
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// Revision 1.2 2001/06/12 15:19:49 rudi
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//
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//
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//
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//
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// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
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// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
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//
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//
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Line 123... |
//
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//
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// Misc Logic
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// Misc Logic
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//
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//
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always @(mem_type or wr_hold or sdram_adr or acs_addr or sram_addr or wb_addr_i)
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always @(mem_type or wr_hold or sdram_adr or acs_addr or sram_addr or wb_addr_i)
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if(mem_type == `MEM_TYPE_SDRAM) mc_addr_d = {9'h0, sdram_adr};
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if(mem_type == `MC_MEM_TYPE_SDRAM) mc_addr_d = {9'h0, sdram_adr};
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else
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else
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if(mem_type == `MEM_TYPE_ACS) mc_addr_d = acs_addr;
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if(mem_type == `MC_MEM_TYPE_ACS) mc_addr_d = acs_addr;
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else
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else
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if((mem_type == `MEM_TYPE_SRAM) & wr_hold) mc_addr_d = sram_addr;
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if((mem_type == `MC_MEM_TYPE_SRAM) & wr_hold) mc_addr_d = sram_addr;
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else mc_addr_d = wb_addr_i[25:2];
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else mc_addr_d = wb_addr_i[25:2];
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assign mc_addr = rfr_ack ? {mc_addr_d[23:11], 1'b1, mc_addr_d[9:0]} : mc_addr_d;
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assign mc_addr = rfr_ack ? {mc_addr_d[23:11], 1'b1, mc_addr_d[9:0]} : mc_addr_d;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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| Line 145... |
Line 151... |
// *** Use same address for write and read ***
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// *** Use same address for write and read ***
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//if(wb_write_go) acs_addr <= #1 wb_addr_i[25:2];
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//if(wb_write_go) acs_addr <= #1 wb_addr_i[25:2];
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//else
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//else
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if(cs_le)
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if(cs_le)
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case(bus_width) // synopsys full_case parallel_case
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case(bus_width) // synopsys full_case parallel_case
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`BW_8: acs_addr <= #1 wb_addr_i[23:0];
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`MC_BW_8: acs_addr <= #1 wb_addr_i[23:0];
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`BW_16: acs_addr <= #1 wb_addr_i[24:1];
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`MC_BW_16: acs_addr <= #1 wb_addr_i[24:1];
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`BW_32: acs_addr <= #1 wb_addr_i[25:2];
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`MC_BW_32: acs_addr <= #1 wb_addr_i[25:2];
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endcase
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endcase
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else
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else
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if(next_adr) acs_addr <= #1 acs_addr_pl1;
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if(next_adr) acs_addr <= #1 acs_addr_pl1;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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Line 172... |
assign sdram_adr[14:13] = bank_adr;
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assign sdram_adr[14:13] = bank_adr;
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always @(posedge clk)
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always @(posedge clk)
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if(wr_cycle ? wb_ack_o : wb_stb_i)
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if(wr_cycle ? wb_ack_o : wb_stb_i)
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casex({bus_width, mem_size}) // synopsys full_case parallel_case
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casex({bus_width, mem_size}) // synopsys full_case parallel_case
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{`BW_8, `MEM_SIZE_64}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
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{`MC_BW_8, `MC_MEM_SIZE_64}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
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{`BW_8, `MEM_SIZE_128}: col_adr <= #1 wb_addr_i[11:2];
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{`MC_BW_8, `MC_MEM_SIZE_128}: col_adr <= #1 wb_addr_i[11:2];
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{`BW_8, `MEM_SIZE_256}: col_adr <= #1 wb_addr_i[11:2];
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{`MC_BW_8, `MC_MEM_SIZE_256}: col_adr <= #1 wb_addr_i[11:2];
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{`BW_16, `MEM_SIZE_64}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
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{`MC_BW_16, `MC_MEM_SIZE_64}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
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{`BW_16, `MEM_SIZE_128}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
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{`MC_BW_16, `MC_MEM_SIZE_128}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
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{`BW_16, `MEM_SIZE_256}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
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{`MC_BW_16, `MC_MEM_SIZE_256}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
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{`BW_32, `MEM_SIZE_64}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
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{`MC_BW_32, `MC_MEM_SIZE_64}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
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{`BW_32, `MEM_SIZE_128}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
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{`MC_BW_32, `MC_MEM_SIZE_128}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
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{`BW_32, `MEM_SIZE_256}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
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{`MC_BW_32, `MC_MEM_SIZE_256}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
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endcase
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endcase
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always @(posedge clk)
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always @(posedge clk)
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if(cs_le)
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if(cs_le)
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begin
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begin
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if(!bas)
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if(!bas)
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casex({bus_width, mem_size}) // synopsys full_case parallel_case
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casex({bus_width, mem_size}) // synopsys full_case parallel_case
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{`BW_8, `MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[24:13]};
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{`MC_BW_8, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[24:13]};
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{`BW_8, `MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[25:14]};
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{`MC_BW_8, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[25:14]};
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{`BW_8, `MEM_SIZE_256}: row_adr <= #1 wb_addr_i[26:14];
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{`MC_BW_8, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[26:14];
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{`BW_16, `MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
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{`MC_BW_16, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
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{`BW_16, `MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[24:13]};
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{`MC_BW_16, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[24:13]};
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{`BW_16, `MEM_SIZE_256}: row_adr <= #1 wb_addr_i[25:13];
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{`MC_BW_16, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[25:13];
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{`BW_32, `MEM_SIZE_64}: row_adr <= #1 {2'h0, wb_addr_i[22:12]};
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{`MC_BW_32, `MC_MEM_SIZE_64}: row_adr <= #1 {2'h0, wb_addr_i[22:12]};
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{`BW_32, `MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
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{`MC_BW_32, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
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{`BW_32, `MEM_SIZE_256}: row_adr <= #1 wb_addr_i[24:12];
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{`MC_BW_32, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[24:12];
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endcase
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endcase
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else
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else
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casex({bus_width, mem_size}) // synopsys full_case parallel_case
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casex({bus_width, mem_size}) // synopsys full_case parallel_case
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{`BW_8, `MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[22:11]};
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{`MC_BW_8, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[22:11]};
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{`BW_8, `MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
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{`MC_BW_8, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
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{`BW_8, `MEM_SIZE_256}: row_adr <= #1 wb_addr_i[24:12];
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{`MC_BW_8, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[24:12];
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{`BW_16, `MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[21:10]};
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{`MC_BW_16, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[21:10]};
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{`BW_16, `MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[22:11]};
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{`MC_BW_16, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[22:11]};
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{`BW_16, `MEM_SIZE_256}: row_adr <= #1 wb_addr_i[23:11];
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{`MC_BW_16, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[23:11];
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{`BW_32, `MEM_SIZE_64}: row_adr <= #1 {2'h0, wb_addr_i[20:10]};
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{`MC_BW_32, `MC_MEM_SIZE_64}: row_adr <= #1 {2'h0, wb_addr_i[20:10]};
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{`BW_32, `MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[21:10]};
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{`MC_BW_32, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[21:10]};
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{`BW_32, `MEM_SIZE_256}: row_adr <= #1 wb_addr_i[22:10];
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{`MC_BW_32, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[22:10];
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endcase
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endcase
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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if(cs_le)
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if(cs_le)
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begin
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begin
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if(!bas)
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if(!bas)
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casex({bus_width, mem_size}) // synopsys full_case parallel_case
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casex({bus_width, mem_size}) // synopsys full_case parallel_case
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{`BW_8, `MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[12:11];
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{`MC_BW_8, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[12:11];
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{`BW_8, `MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[13:12];
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{`MC_BW_8, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[13:12];
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{`BW_8, `MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[13:12];
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{`MC_BW_8, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[13:12];
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{`BW_16, `MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[11:10];
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{`MC_BW_16, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[11:10];
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{`BW_16, `MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[12:11];
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{`MC_BW_16, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[12:11];
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{`BW_16, `MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[12:11];
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{`MC_BW_16, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[12:11];
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{`BW_32, `MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[11:10];
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{`MC_BW_32, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[11:10];
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{`BW_32, `MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[11:10];
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{`MC_BW_32, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[11:10];
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{`BW_32, `MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[11:10];
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{`MC_BW_32, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[11:10];
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endcase
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endcase
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else
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else
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casex({bus_width, mem_size}) // synopsys full_case parallel_case
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casex({bus_width, mem_size}) // synopsys full_case parallel_case
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{`BW_8, `MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[24:23];
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{`MC_BW_8, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[24:23];
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{`BW_8, `MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[25:24];
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{`MC_BW_8, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[25:24];
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{`BW_8, `MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[26:25];
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{`MC_BW_8, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[26:25];
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{`BW_16, `MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[23:22];
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{`MC_BW_16, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[23:22];
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{`BW_16, `MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[24:23];
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{`MC_BW_16, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[24:23];
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{`BW_16, `MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[25:24];
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{`MC_BW_16, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[25:24];
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{`BW_32, `MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[22:21];
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{`MC_BW_32, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[22:21];
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{`BW_32, `MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[23:22];
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{`MC_BW_32, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[23:22];
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{`BW_32, `MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[24:23];
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{`MC_BW_32, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[24:23];
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endcase
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endcase
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end
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end
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always @(bus_width or mem_size)
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always @(bus_width or mem_size)
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casex({bus_width, mem_size}) // synopsys full_case parallel_case
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casex({bus_width, mem_size}) // synopsys full_case parallel_case
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{`BW_8, `MEM_SIZE_64}: page_size = 11'd512;
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{`MC_BW_8, `MC_MEM_SIZE_64}: page_size = 11'd512;
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{`BW_8, `MEM_SIZE_128}: page_size = 11'd1024;
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{`MC_BW_8, `MC_MEM_SIZE_128}: page_size = 11'd1024;
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{`BW_8, `MEM_SIZE_256}: page_size = 11'd1024;
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{`MC_BW_8, `MC_MEM_SIZE_256}: page_size = 11'd1024;
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{`BW_16, `MEM_SIZE_64}: page_size = 11'd256;
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{`MC_BW_16, `MC_MEM_SIZE_64}: page_size = 11'd256;
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{`BW_16, `MEM_SIZE_128}: page_size = 11'd512;
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{`MC_BW_16, `MC_MEM_SIZE_128}: page_size = 11'd512;
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{`BW_16, `MEM_SIZE_256}: page_size = 11'd512;
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{`MC_BW_16, `MC_MEM_SIZE_256}: page_size = 11'd512;
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{`BW_32, `MEM_SIZE_64}: page_size = 11'd256;
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{`MC_BW_32, `MC_MEM_SIZE_64}: page_size = 11'd256;
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{`BW_32, `MEM_SIZE_128}: page_size = 11'd256;
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{`MC_BW_32, `MC_MEM_SIZE_128}: page_size = 11'd256;
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{`BW_32, `MEM_SIZE_256}: page_size = 11'd256;
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{`MC_BW_32, `MC_MEM_SIZE_256}: page_size = 11'd256;
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endcase
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endcase
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endmodule
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endmodule
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No newline at end of file
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