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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_cs_rf.v,v 1.1 2001-07-29 07:34:41 rudi Exp $
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// $Id: mc_cs_rf.v,v 1.2 2001-08-10 08:16:21 rudi Exp $
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//
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//
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// $Date: 2001-07-29 07:34:41 $
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// $Date: 2001-08-10 08:16:21 $
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// $Revision: 1.1 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/07/29 07:34:41 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Fixed several minor bugs
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//
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// Revision 1.3 2001/06/12 15:19:49 rudi
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// Revision 1.3 2001/06/12 15:19:49 rudi
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//
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//
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//
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//
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// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
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// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
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//
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//
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Line 128... |
//
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//
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assign sel = addr[6:3] == reg_select[3:0];
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assign sel = addr[6:3] == reg_select[3:0];
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always @(posedge clk)
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always @(posedge clk)
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if(!rst) csc <= #1 (this_cs[2:0] == `DEF_SEL) ?
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if(!rst) csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?
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{26'h0, poc[1:0], 1'b0, poc[3:2], (poc[3:2] != 2'b00)} : 32'h0;
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{26'h0, poc[1:0], 1'b0, poc[3:2], (poc[3:2] != 2'b00)} : 32'h0;
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else
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else
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if(rf_we & sel & !addr[2]) csc <= #1 din;
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if(rf_we & sel & !addr[2]) csc <= #1 din;
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always @(posedge clk)
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always @(posedge clk)
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if(!rst) tms <= #1 (this_cs[2:0] == `DEF_SEL) ? `DEF_POR_TMS :
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if(!rst) tms <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?
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32'h0;
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`MC_DEF_POR_TMS : 32'h0;
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else
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else
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if(rf_we & sel & addr[2]) tms <= #1 din;
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if(rf_we & sel & addr[2]) tms <= #1 din;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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Line 149... |
lmr_req_we <= #1 rf_we & sel & addr[2];
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lmr_req_we <= #1 rf_we & sel & addr[2];
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) lmr_req <= #1 1'b0;
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if(!rst) lmr_req <= #1 1'b0;
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else
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else
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if(lmr_req_we & (csc[3:1] == `MEM_TYPE_SDRAM))
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if(lmr_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM))
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lmr_req <= #1 inited;
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lmr_req <= #1 inited;
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else
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else
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if(lmr_ack) lmr_req <= #1 1'b0;
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if(lmr_ack) lmr_req <= #1 1'b0;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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| Line 158... |
Line 164... |
init_req_we <= #1 rf_we & sel & !addr[2];
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init_req_we <= #1 rf_we & sel & !addr[2];
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) init_req <= #1 1'b0;
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if(!rst) init_req <= #1 1'b0;
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else
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else
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if(init_req_we & (csc[3:1] == `MEM_TYPE_SDRAM) & csc[0] & !inited)
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if(init_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM) & csc[0] & !inited)
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init_req <= #1 1'b1;
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init_req <= #1 1'b1;
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else
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else
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if(init_ack) init_req <= #1 1'b0;
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if(init_ack) init_req <= #1 1'b0;
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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