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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_defines.v,v 1.3 2001-09-10 13:44:17 rudi Exp $
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// $Id: mc_defines.v,v 1.4 2001-11-29 02:16:28 rudi Exp $
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//
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//
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// $Date: 2001-09-10 13:44:17 $
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// $Date: 2001-11-29 02:16:28 $
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// $Revision: 1.3 $
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// $Revision: 1.4 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/09/10 13:44:17 rudi
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// *** empty log message ***
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//
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// Revision 1.2 2001/08/10 08:16:21 rudi
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// Revision 1.2 2001/08/10 08:16:21 rudi
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//
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//
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// - Changed IO names to be more clear.
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Uniquifyed define names to be core specific.
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// - Removed "Refresh Early" configuration
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// - Removed "Refresh Early" configuration
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// 2) Fixed several minor bugs
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// 2) Fixed several minor bugs
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//
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//
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// Revision 1.3 2001/06/12 15:19:49 rudi
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// Revision 1.3 2001/06/12 15:19:49 rudi
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//
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//
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//
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//
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// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
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// Minor changes after running lint, and a small bug
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// fix reading csr and ba_mask registers.
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//
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//
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// Revision 1.2 2001/06/03 11:37:17 rudi
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// Revision 1.2 2001/06/03 11:37:17 rudi
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//
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//
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//
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//
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// 1) Fixed Chip Select Mask Register
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// 1) Fixed Chip Select Mask Register
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//
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//
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// This are the default Power-On Reset values for Chip Select
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// This are the default Power-On Reset values for Chip Select
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//
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//
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// This will be defined by the run script for my test bench ...
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//`define RUDIS_TB 1
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// Defines which chip select is used for Power On booting
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// Defines which chip select is used for Power On booting
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`define MC_DEF_SEL 3'h1
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// To run my default testbench default boot CS must be 3 !!!
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`ifdef RUDIS_TB
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`define MC_DEF_SEL 3'h3
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`else
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`define MC_DEF_SEL 3'h0
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`endif
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// Defines the default (reset) TMS value for the DEF_SEL chip select
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// Defines the default (reset) TMS value for the DEF_SEL chip select
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`define MC_DEF_POR_TMS 32'hffff_ffff
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`define MC_DEF_POR_TMS 32'hffff_ffff
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//`define MC_HAVE_CS5 1
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//`define MC_HAVE_CS5 1
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//`define MC_HAVE_CS6 1
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//`define MC_HAVE_CS6 1
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//`define MC_HAVE_CS7 1
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//`define MC_HAVE_CS7 1
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// To run my default testbench those need to there !!!
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`ifdef RUDIS_TB
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`define MC_HAVE_CS2 1
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`define MC_HAVE_CS3 1
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`define MC_HAVE_CS4 1
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`define MC_HAVE_CS5 1
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`endif
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//
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//
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// Init Refresh
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// Init Refresh
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//
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//
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// Number of Refresh Cycles to perform during SDRAM initialization.
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// Number of Refresh Cycles to perform during SDRAM initialization.
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