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[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_defines.v] - Diff between revs 18 and 19
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_defines.v,v 1.5 2001-12-11 02:47:19 rudi Exp $
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// $Id: mc_defines.v,v 1.6 2001-12-12 06:35:15 rudi Exp $
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//
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//
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// $Date: 2001-12-11 02:47:19 $
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// $Date: 2001-12-12 06:35:15 $
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// $Revision: 1.5 $
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// $Revision: 1.6 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2001/12/11 02:47:19 rudi
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//
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// - Made some changes not to expect clock during reset ...
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//
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// Revision 1.4 2001/11/29 02:16:28 rudi
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// Revision 1.4 2001/11/29 02:16:28 rudi
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//
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//
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//
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//
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// - More Synthesis cleanup, mostly for speed
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// - More Synthesis cleanup, mostly for speed
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// - Several bug fixes
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// - Several bug fixes
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//
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//
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// This are the default Power-On Reset values for Chip Select
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// This are the default Power-On Reset values for Chip Select
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//
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//
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// This will be defined by the run script for my test bench ...
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// This will be defined by the run script for my test bench ...
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`define RUDIS_TB 1
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//`define RUDIS_TB 1
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// Defines which chip select is used for Power On booting
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// Defines which chip select is used for Power On booting
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// To run my default testbench default boot CS must be 3 !!!
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// To run my default testbench default boot CS must be 3 !!!
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`ifdef RUDIS_TB
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`ifdef RUDIS_TB
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