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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
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//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Rudolf Usselmann ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_defines.v,v 1.6 2001-12-12 06:35:15 rudi Exp $
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// $Id: mc_defines.v,v 1.7 2002-01-21 13:08:52 rudi Exp $
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//
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//
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// $Date: 2001-12-12 06:35:15 $
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// $Date: 2002-01-21 13:08:52 $
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// $Revision: 1.6 $
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// $Revision: 1.7 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2001/12/12 06:35:15 rudi
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// *** empty log message ***
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//
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// Revision 1.5 2001/12/11 02:47:19 rudi
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// Revision 1.5 2001/12/11 02:47:19 rudi
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//
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//
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// - Made some changes not to expect clock during reset ...
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// - Made some changes not to expect clock during reset ...
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//
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//
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// Revision 1.4 2001/11/29 02:16:28 rudi
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// Revision 1.4 2001/11/29 02:16:28 rudi
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| Line 109... |
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//
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//
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// This define selects how the WISHBONE interface determines if
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// This define selects how the WISHBONE interface determines if
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// the internal register file is selected.
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// the internal register file is selected.
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// This should be a simple address decoder. "wb_addr_i" is the
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// This should be a simple address decoder. "wb_addr_i" is the
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// WISHBONE address bus (32 bits wide).
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// WISHBONE address bus (32 bits wide).
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//`define MC_REG_SEL (wb_addr_i[31:29] == 3'h6)
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`define MC_REG_SEL (wb_addr_i[31:29] == 3'b011)
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`define MC_REG_SEL (wb_addr_i[31:29] == 3'b011)
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// This define selects how the WISHBONE interface determines if
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// This define selects how the WISHBONE interface determines if
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// the memory is selected.
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// the memory is selected.
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// This should be a simple address decoder. "wb_addr_i" is the
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// This should be a simple address decoder. "wb_addr_i" is the
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//
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//
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// This are the default Power-On Reset values for Chip Select
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// This are the default Power-On Reset values for Chip Select
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//
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//
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// This will be defined by the run script for my test bench ...
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// This will be defined by the run script for my test bench ...
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// Alternatively force here for synthesis ...
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//`define RUDIS_TB 1
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//`define RUDIS_TB 1
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// Defines which chip select is used for Power On booting
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// Defines which chip select is used for Power On booting
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// To run my default testbench default boot CS must be 3 !!!
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// To run my default testbench default boot CS must be 3 !!!
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