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[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_dp.v] - Diff between revs 8 and 12

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Rev 8 Rev 12
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////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
 
 
//  CVS Log
//  CVS Log
//
//
//  $Id: mc_dp.v,v 1.2 2001-08-10 08:16:21 rudi Exp $
//  $Id: mc_dp.v,v 1.3 2001-09-24 00:38:21 rudi Exp $
//
//
//  $Date: 2001-08-10 08:16:21 $
//  $Date: 2001-09-24 00:38:21 $
//  $Revision: 1.2 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Author: rudi $
//  $Locker:  $
//  $Locker:  $
//  $State: Exp $
//  $State: Exp $
//
//
// Change History:
// Change History:
//               $Log: not supported by cvs2svn $
//               $Log: not supported by cvs2svn $
 
//               Revision 1.2  2001/08/10 08:16:21  rudi
 
//
 
//               - Changed IO names to be more clear.
 
//               - Uniquifyed define names to be core specific.
 
//               - Removed "Refresh Early" configuration
 
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//
//
//               1) Changed Directory Structure
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//               2) Fixed several minor bugs
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        else                                    wb_data_o <= #1 mc_data_d;
        else                                    wb_data_o <= #1 mc_data_d;
 
 
always @(posedge clk)
always @(posedge clk)
        mc_data_del <= #1 {mc_dp_i, mc_data_i};
        mc_data_del <= #1 {mc_dp_i, mc_data_i};
 
 
assign rd_fifo_clr = rst & wb_cyc_i;
assign rd_fifo_clr = !rst & wb_cyc_i;
assign re = mem_wb_ack_o & wb_read_go;
assign re = mem_wb_ack_o & wb_read_go;
 
 
mc_rd_fifo u0(
mc_rd_fifo u0(
        .clk(   clk                     ),
        .clk(   clk                     ),
        .rst(   rd_fifo_clr             ),
        .rst(   rd_fifo_clr             ),

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