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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_dp.v,v 1.4 2001-11-29 02:16:28 rudi Exp $
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// $Id: mc_dp.v,v 1.5 2001-12-11 02:47:19 rudi Exp $
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//
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//
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// $Date: 2001-11-29 02:16:28 $
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// $Date: 2001-12-11 02:47:19 $
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// $Revision: 1.4 $
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// $Revision: 1.5 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2001/11/29 02:16:28 rudi
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//
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//
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// - More Synthesis cleanup, mostly for speed
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// - Several bug fixes
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// - Changed code to avoid auto-precharge and
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// burst-terminate combinations (apparently illegal ?)
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// Now we will do a manual precharge ...
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//
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// Revision 1.3 2001/09/24 00:38:21 rudi
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// Revision 1.3 2001/09/24 00:38:21 rudi
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//
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//
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// Changed Reset to be active high and async.
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// Changed Reset to be active high and async.
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//
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//
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// Revision 1.2 2001/08/10 08:16:21 rudi
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// Revision 1.2 2001/08/10 08:16:21 rudi
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always @(mem_type or rd_fifo_out or mc_data_d)
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always @(mem_type or rd_fifo_out or mc_data_d)
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if( (mem_type == `MC_MEM_TYPE_SDRAM) |
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if( (mem_type == `MC_MEM_TYPE_SDRAM) |
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(mem_type == `MC_MEM_TYPE_SRAM) ) wb_data_o = rd_fifo_out[31:0];
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(mem_type == `MC_MEM_TYPE_SRAM) ) wb_data_o = rd_fifo_out[31:0];
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else wb_data_o = mc_data_d;
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else wb_data_o = mc_data_d;
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assign rd_fifo_clr = !(rst | !wb_cyc_i | (wb_we_i & wb_stb_i) );
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//assign rd_fifo_clr = !(rst | !wb_cyc_i | (wb_we_i & wb_stb_i) );
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assign rd_fifo_clr = !wb_cyc_i | (wb_we_i & wb_stb_i);
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assign re = wb_ack_o & wb_read_go;
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assign re = wb_ack_o & wb_read_go;
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mc_rd_fifo u0(
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mc_rd_fifo u0(
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.clk( clk ),
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.clk( clk ),
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.rst( rd_fifo_clr ),
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.rst( rst ),
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.clr( rd_fifo_clr ),
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.din( mc_data_del ),
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.din( mc_data_del ),
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.we( dv ),
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.we( dv ),
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.dout( rd_fifo_out ),
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.dout( rd_fifo_out ),
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.re( re )
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.re( re )
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);
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);
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