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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_dp.v,v 1.1 2001-07-29 07:34:41 rudi Exp $
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// $Id: mc_dp.v,v 1.2 2001-08-10 08:16:21 rudi Exp $
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//
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//
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// $Date: 2001-07-29 07:34:41 $
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// $Date: 2001-08-10 08:16:21 $
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// $Revision: 1.1 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/07/29 07:34:41 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Fixed several minor bugs
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//
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// Revision 1.2 2001/06/03 11:37:17 rudi
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// Revision 1.2 2001/06/03 11:37:17 rudi
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//
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//
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//
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//
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// 1) Fixed Chip Select Mask Register
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// 1) Fixed Chip Select Mask Register
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// - Power On Value is now all ones
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// - Power On Value is now all ones
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Line 136... |
//
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//
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// WB READ Data Path
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// WB READ Data Path
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//
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//
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always @(posedge clk)
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always @(posedge clk)
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if(mem_type == `MEM_TYPE_SDRAM) wb_data_o <= #1 rd_fifo_out[31:0];
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if(mem_type == `MC_MEM_TYPE_SDRAM) wb_data_o <= #1 rd_fifo_out[31:0];
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else
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else
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if(mem_type == `MEM_TYPE_SRAM) wb_data_o <= #1 rd_fifo_out[31:0];
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if(mem_type == `MC_MEM_TYPE_SRAM) wb_data_o <= #1 rd_fifo_out[31:0];
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else wb_data_o <= #1 mc_data_d;
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else wb_data_o <= #1 mc_data_d;
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always @(posedge clk)
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always @(posedge clk)
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mc_data_del <= #1 {mc_dp_i, mc_data_i};
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mc_data_del <= #1 {mc_dp_i, mc_data_i};
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Line 162... |
//
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//
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// WB WRITE Data Path
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// WB WRITE Data Path
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//
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//
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always @(posedge clk)
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always @(posedge clk)
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if(mem_wb_ack_o | (mem_type != `MEM_TYPE_SDRAM) )
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if(mem_wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) )
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mc_data_o <= #1 wb_data_i;
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mc_data_o <= #1 wb_data_i;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Read Data Packing
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// Read Data Packing
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Line 174... |
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always @(posedge clk)
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always @(posedge clk)
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if(pack_le0) byte0 <= #1 mc_data_i[7:0];
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if(pack_le0) byte0 <= #1 mc_data_i[7:0];
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always @(posedge clk)
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always @(posedge clk)
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if(pack_le1 & (bus_width == `BW_8)) byte1 <= #1 mc_data_i[7:0];
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if(pack_le1 & (bus_width == `MC_BW_8)) byte1 <= #1 mc_data_i[7:0];
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else
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else
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if(pack_le0 & (bus_width == `BW_16)) byte1 <= #1 mc_data_i[15:8];
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if(pack_le0 & (bus_width == `MC_BW_16)) byte1 <= #1 mc_data_i[15:8];
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always @(posedge clk)
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always @(posedge clk)
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if(pack_le2) byte2 <= #1 mc_data_i[7:0];
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if(pack_le2) byte2 <= #1 mc_data_i[7:0];
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always @(bus_width or mc_data_i or byte0 or byte1 or byte2)
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always @(bus_width or mc_data_i or byte0 or byte1 or byte2)
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if(bus_width == `BW_8) mc_data_d = {mc_data_i[7:0], byte2, byte1, byte0};
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if(bus_width == `MC_BW_8) mc_data_d = {mc_data_i[7:0], byte2, byte1, byte0};
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else
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else
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if(bus_width == `BW_16) mc_data_d = {mc_data_i[15:0], byte1, byte0};
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if(bus_width == `MC_BW_16) mc_data_d = {mc_data_i[15:0], byte1, byte0};
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else mc_data_d = mc_data_i;
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else mc_data_d = mc_data_i;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Parity Generation
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// Parity Generation
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//
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//
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always @(posedge clk)
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always @(posedge clk)
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if(mem_wb_ack_o | (mem_type != `MEM_TYPE_SDRAM) )
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if(mem_wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) )
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mc_dp_o <= #1 { ^wb_data_i[31:24], ^wb_data_i[23:16],
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mc_dp_o <= #1 { ^wb_data_i[31:24], ^wb_data_i[23:16],
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^wb_data_i[15:08], ^wb_data_i[07:00] };
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^wb_data_i[15:08], ^wb_data_i[07:00] };
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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