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[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_mem_if.v] - Diff between revs 9 and 12

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Line 36... Line 36...
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
 
 
//  CVS Log
//  CVS Log
//
//
//  $Id: mc_mem_if.v,v 1.2 2001-09-02 02:28:28 rudi Exp $
//  $Id: mc_mem_if.v,v 1.3 2001-09-24 00:38:21 rudi Exp $
//
//
//  $Date: 2001-09-02 02:28:28 $
//  $Date: 2001-09-24 00:38:21 $
//  $Revision: 1.2 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Author: rudi $
//  $Locker:  $
//  $Locker:  $
//  $State: Exp $
//  $State: Exp $
//
//
// Change History:
// Change History:
//               $Log: not supported by cvs2svn $
//               $Log: not supported by cvs2svn $
 
//               Revision 1.2  2001/09/02 02:28:28  rudi
 
//
 
//               Many fixes for minor bugs that showed up in gate level simulations.
 
//
//               Revision 1.1  2001/07/29 07:34:41  rudi
//               Revision 1.1  2001/07/29 07:34:41  rudi
//
//
//
//
//               1) Changed Directory Structure
//               1) Changed Directory Structure
//               2) Fixed several minor bugs
//               2) Fixed several minor bugs
Line 185... Line 189...
        mc_ack_r <= #1 mc_ack;
        mc_ack_r <= #1 mc_ack;
 
 
always @(posedge mc_clk)
always @(posedge mc_clk)
        mc_bg <= #1 mc_bg_d;
        mc_bg <= #1 mc_bg_d;
 
 
always @(posedge mc_clk)
always @(posedge mc_clk or posedge rst)
        mc_data_oe <= #1 data_oe & !susp_sel & mc_c_oe & rst;
        if(rst)         mc_data_oe <= #1 1'b0;
 
        else            mc_data_oe <= #1 data_oe & !susp_sel & mc_c_oe;
 
 
always @(posedge mc_clk)
always @(posedge mc_clk)
        mc_data_o <= #1 mc_data_od;
        mc_data_o <= #1 mc_data_od;
 
 
always @(posedge mc_clk)
always @(posedge mc_clk)
Line 206... Line 211...
always @(posedge mc_clk)
always @(posedge mc_clk)
        mc_dqm <= #1    susp_sel ? 4'hf :
        mc_dqm <= #1    susp_sel ? 4'hf :
                        data_oe ? ~mc_dqm_r :
                        data_oe ? ~mc_dqm_r :
                        (wb_cycle & !wr_cycle) ? 4'h0 : 4'hf;
                        (wb_cycle & !wr_cycle) ? 4'h0 : 4'hf;
 
 
always @(posedge mc_clk or negedge rst)
always @(posedge mc_clk or posedge rst)
        if(!rst)        mc_oe_ <= #1 1'b1;
        if(rst)         mc_oe_ <= #1 1'b1;
        else            mc_oe_ <= #1 oe_ | susp_sel;
        else            mc_oe_ <= #1 oe_ | susp_sel;
 
 
always @(posedge mc_clk)
always @(posedge mc_clk)
        mc_we_ <= #1 we_;
        mc_we_ <= #1 we_;
 
 
Line 231... Line 236...
                                lmr_sel ? spec_req_cs[n] :
                                lmr_sel ? spec_req_cs[n] :
                                cs[n]
                                cs[n]
                        ));
                        ));
*/
*/
 
 
always @(posedge mc_clk or negedge rst)
always @(posedge mc_clk or posedge rst)
        if(!rst)        mc_cs_[0] <= #1 1'b1;
        if(rst)         mc_cs_[0] <= #1 1'b1;
        else
        else
        mc_cs_[0] <= #1 ~(cs_en & (
        mc_cs_[0] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[0] :
                                (rfr_ack | susp_sel) ? cs_need_rfr[0] :
                                lmr_sel ? spec_req_cs[0] :
                                lmr_sel ? spec_req_cs[0] :
                                cs[0]
                                cs[0]
                        ));
                        ));
 
 
always @(posedge mc_clk or negedge rst)
always @(posedge mc_clk or posedge rst)
        if(!rst)        mc_cs_[1] <= #1 1'b1;
        if(rst)         mc_cs_[1] <= #1 1'b1;
        else
        else
           mc_cs_[1] <= #1 ~(cs_en & (
           mc_cs_[1] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[1] :
                                (rfr_ack | susp_sel) ? cs_need_rfr[1] :
                                lmr_sel ? spec_req_cs[1] :
                                lmr_sel ? spec_req_cs[1] :
                                cs[1]
                                cs[1]
                        ));
                        ));
 
 
always @(posedge mc_clk or negedge rst)
always @(posedge mc_clk or posedge rst)
        if(!rst)        mc_cs_[2] <= #1 1'b1;
        if(rst)         mc_cs_[2] <= #1 1'b1;
        else
        else
           mc_cs_[2] <= #1 ~(cs_en & (
           mc_cs_[2] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[2] :
                                (rfr_ack | susp_sel) ? cs_need_rfr[2] :
                                lmr_sel ? spec_req_cs[2] :
                                lmr_sel ? spec_req_cs[2] :
                                cs[2]
                                cs[2]
                        ));
                        ));
 
 
always @(posedge mc_clk or negedge rst)
always @(posedge mc_clk or posedge rst)
        if(!rst)        mc_cs_[3] <= #1 1'b1;
        if(rst)         mc_cs_[3] <= #1 1'b1;
        else
        else
           mc_cs_[3] <= #1 ~(cs_en & (
           mc_cs_[3] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[3] :
                                (rfr_ack | susp_sel) ? cs_need_rfr[3] :
                                lmr_sel ? spec_req_cs[3] :
                                lmr_sel ? spec_req_cs[3] :
                                cs[3]
                                cs[3]
                        ));
                        ));
 
 
always @(posedge mc_clk or negedge rst)
always @(posedge mc_clk or posedge rst)
        if(!rst)        mc_cs_[4] <= #1 1'b1;
        if(rst)         mc_cs_[4] <= #1 1'b1;
        else
        else
           mc_cs_[4] <= #1 ~(cs_en & (
           mc_cs_[4] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[4] :
                                (rfr_ack | susp_sel) ? cs_need_rfr[4] :
                                lmr_sel ? spec_req_cs[4] :
                                lmr_sel ? spec_req_cs[4] :
                                cs[4]
                                cs[4]
                        ));
                        ));
 
 
always @(posedge mc_clk or negedge rst)
always @(posedge mc_clk or posedge rst)
        if(!rst)        mc_cs_[5] <= #1 1'b1;
        if(rst)         mc_cs_[5] <= #1 1'b1;
        else
        else
           mc_cs_[5] <= #1 ~(cs_en & (
           mc_cs_[5] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[5] :
                                (rfr_ack | susp_sel) ? cs_need_rfr[5] :
                                lmr_sel ? spec_req_cs[5] :
                                lmr_sel ? spec_req_cs[5] :
                                cs[5]
                                cs[5]
                        ));
                        ));
 
 
always @(posedge mc_clk or negedge rst)
always @(posedge mc_clk or posedge rst)
        if(!rst)        mc_cs_[6] <= #1 1'b1;
        if(rst)         mc_cs_[6] <= #1 1'b1;
        else
        else
           mc_cs_[6] <= #1 ~(cs_en & (
           mc_cs_[6] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[6] :
                                (rfr_ack | susp_sel) ? cs_need_rfr[6] :
                                lmr_sel ? spec_req_cs[6] :
                                lmr_sel ? spec_req_cs[6] :
                                cs[6]
                                cs[6]
                        ));
                        ));
 
 
always @(posedge mc_clk or negedge rst)
always @(posedge mc_clk or posedge rst)
        if(!rst)        mc_cs_[7] <= #1 1'b1;
        if(rst)         mc_cs_[7] <= #1 1'b1;
        else
        else
           mc_cs_[7] <= #1 ~(cs_en & (
           mc_cs_[7] <= #1 ~(cs_en & (
                                (rfr_ack | susp_sel) ? cs_need_rfr[7] :
                                (rfr_ack | susp_sel) ? cs_need_rfr[7] :
                                lmr_sel ? spec_req_cs[7] :
                                lmr_sel ? spec_req_cs[7] :
                                cs[7]
                                cs[7]

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