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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_rd_fifo.v,v 1.2 2001-11-29 02:16:28 rudi Exp $
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// $Id: mc_rd_fifo.v,v 1.3 2001-12-11 02:47:19 rudi Exp $
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//
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//
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// $Date: 2001-11-29 02:16:28 $
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// $Date: 2001-12-11 02:47:19 $
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// $Revision: 1.2 $
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// $Revision: 1.3 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/11/29 02:16:28 rudi
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//
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//
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// - More Synthesis cleanup, mostly for speed
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// - Several bug fixes
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// - Changed code to avoid auto-precharge and
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// burst-terminate combinations (apparently illegal ?)
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// Now we will do a manual precharge ...
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//
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// Revision 1.1 2001/07/29 07:34:41 rudi
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// Revision 1.1 2001/07/29 07:34:41 rudi
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//
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//
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//
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//
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// 1) Changed Directory Structure
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// 1) Changed Directory Structure
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// 2) Fixed several minor bugs
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// 2) Fixed several minor bugs
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//
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//
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//
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//
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`include "mc_defines.v"
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`include "mc_defines.v"
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module mc_rd_fifo(clk, rst, din, we, dout, re);
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module mc_rd_fifo(clk, rst, clr, din, we, dout, re);
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input clk, rst;
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input clk, rst, clr;
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input [35:0] din;
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input [35:0] din;
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input we;
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input we;
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output [35:0] dout;
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output [35:0] dout;
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input re;
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input re;
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reg [3:0] rd_adr, wr_adr;
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reg [3:0] rd_adr, wr_adr;
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reg [35:0] r0, r1, r2, r3;
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reg [35:0] r0, r1, r2, r3;
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reg [35:0] dout;
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reg [35:0] dout;
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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if(!rst) rd_adr <= #1 4'h1;
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if(rst) rd_adr <= #1 4'h1;
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else
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if(clr) rd_adr <= #1 4'h1;
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else
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else
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if(re) rd_adr <= #1 {rd_adr[2:0], rd_adr[3]};
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if(re) rd_adr <= #1 {rd_adr[2:0], rd_adr[3]};
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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if(!rst) wr_adr <= #1 4'h1;
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if(rst) wr_adr <= #1 4'h1;
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else
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if(clr) wr_adr <= #1 4'h1;
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else
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else
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if(we) wr_adr <= #1 {wr_adr[2:0], wr_adr[3]};
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if(we) wr_adr <= #1 {wr_adr[2:0], wr_adr[3]};
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always @(posedge clk)
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always @(posedge clk)
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if(we & wr_adr[0]) r0 <= #1 din;
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if(we & wr_adr[0]) r0 <= #1 din;
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