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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_rf.v,v 1.2 2001-08-10 08:16:21 rudi Exp $
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// $Id: mc_rf.v,v 1.3 2001-09-24 00:38:21 rudi Exp $
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//
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//
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// $Date: 2001-08-10 08:16:21 $
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// $Date: 2001-09-24 00:38:21 $
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// $Revision: 1.2 $
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// $Revision: 1.3 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/08/10 08:16:21 rudi
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//
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Removed "Refresh Early" configuration
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//
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// Revision 1.1 2001/07/29 07:34:41 rudi
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// Revision 1.1 2001/07/29 07:34:41 rudi
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//
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//
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//
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//
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// 1) Changed Directory Structure
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// 1) Changed Directory Structure
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// 2) Fixed several minor bugs
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// 2) Fixed several minor bugs
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Line 183... |
wire cs4, cs5, cs6, cs7;
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wire cs4, cs5, cs6, cs7;
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wire wp_err0, wp_err1, wp_err2, wp_err3;
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wire wp_err0, wp_err1, wp_err2, wp_err3;
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wire wp_err4, wp_err5, wp_err6, wp_err7;
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wire wp_err4, wp_err5, wp_err6, wp_err7;
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reg wp_err;
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reg wp_err;
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wire lmr_req7, lmr_req6, lmr_req5, lmr_req4;
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wire lmr_req7, lmr_req6, lmr_req5, lmr_req4;
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wire lmr_req3, lmr_req2, lmr_req1, lmr_req0;
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wire lmr_req3, lmr_req2, lmr_req1, lmr_req0;
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wire lmr_ack7, lmr_ack6, lmr_ack5, lmr_ack4;
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wire lmr_ack7, lmr_ack6, lmr_ack5, lmr_ack4;
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wire lmr_ack3, lmr_ack2, lmr_ack1, lmr_ack0;
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wire lmr_ack3, lmr_ack2, lmr_ack1, lmr_ack0;
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Line 248... |
// WISHBONE Register Write logic
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// WISHBONE Register Write logic
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//
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//
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assign rf_we = `MC_REG_SEL & wb_we_i & wb_cyc_i & wb_stb_i;
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assign rf_we = `MC_REG_SEL & wb_we_i & wb_cyc_i & wb_stb_i;
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always @(posedge clk or negedge rst)
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always @(posedge clk or posedge rst)
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if(!rst) csr_r2 <= #1 8'h0;
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if(rst) csr_r2 <= #1 8'h0;
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else
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else
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if(rf_we & (wb_addr_i[6:2] == 5'h0) )
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if(rf_we & (wb_addr_i[6:2] == 5'h0) )
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csr_r2 <= #1 wb_data_i[31:24];
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csr_r2 <= #1 wb_data_i[31:24];
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always @(posedge clk or negedge rst)
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always @(posedge clk or posedge rst)
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if(!rst) csr_r[10:1] <= #1 10'h0;
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if(rst) csr_r[10:1] <= #1 10'h0;
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else
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else
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if(rf_we & (wb_addr_i[6:2] == 5'h0) )
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if(rf_we & (wb_addr_i[6:2] == 5'h0) )
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csr_r[10:1] <= #1 wb_data_i[10:1];
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csr_r[10:1] <= #1 wb_data_i[10:1];
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always @(posedge clk)
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always @(posedge clk)
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Line 267... |
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assign mc_vpen = csr_r[1];
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assign mc_vpen = csr_r[1];
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assign fs = csr_r[2];
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assign fs = csr_r[2];
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assign rfr_ps_val = csr_r2[7:0];
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assign rfr_ps_val = csr_r2[7:0];
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always @(posedge clk or negedge rst)
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always @(posedge clk or posedge rst)
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if(!rst) csc_mask_r <= #1 11'h7ff;
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if(rst) csc_mask_r <= #1 11'h7ff;
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else
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else
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if(rf_we & (wb_addr_i[6:2] == 5'h2) )
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if(rf_we & (wb_addr_i[6:2] == 5'h2) )
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csc_mask_r <= #1 wb_data_i[10:0];
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csc_mask_r <= #1 wb_data_i[10:0];
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always @(posedge clk)
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always @(posedge clk)
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if(!rst) poc <= #1 mc_data_i;
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if(rst) poc <= #1 mc_data_i;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// WISHBONE Register Ack logic
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// WISHBONE Register Ack logic
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//
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//
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